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STM32G071KBU3TR (UFQFPN-32(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32G071KBU3TR

STID: C6689588UFQFPN-32(5x5) · 33 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32G071KBU3TR (UFQFPN-32(5x5))1PB92PC14 - OSC3233V34VDD/VDDA5VSS/VSSA6PF2 NRST -7PA08PA19PA210PA311PA412PA513PA614PA715PB016PB117PB233EP32PB831PB730PB629PB528PB427PB326PA1525PA14BOOT0 -24PA1323PA12 [PA10]22PA11 [PA9]21PA1020PC619PA918PA8Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=5.00mm · Pitch e=0.50mmD=5.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI)
2PC14 - OSC32_IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)
33V3Power3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4VDD/VDDAPowerPower Supply Input (VDD/VDDA — 3.3V VDD (Max 4.0V))
5VSS/VSSAGNDGround Reference Pin (VSS/VSSA)
6PF2 NRST -I/OMultiplexed I/O & Peripheral Pin PF2 NRST - (RTC/CLK)
7PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, SPI, PWM)
8PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, SPI, PWM)
9PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, SPI)
10PA3I/OMultiplexed I/O & Peripheral Pin PA3 (SPI, PWM)
11PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, ADC, RTC/CLK)
12PA5I/OMultiplexed I/O & Peripheral Pin PA5 (UART, SPI, ADC, PWM)
13PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC, PWM)
14PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
15PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC, PWM)
16PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, PWM)
17PB2I/OMultiplexed I/O & Peripheral Pin PB2 (SPI)
18PA8I/OMultiplexed I/O & Peripheral Pin PA8 (SPI, PWM, RTC/CLK)
19PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, PWM, RTC/CLK)
20PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
21PA10I/OMultiplexed I/O & Peripheral Pin PA10 (SPI, I2C, PWM)
22PA11 [PA9]I/OMultiplexed I/O & Peripheral Pin PA11 [PA9] (UART, SPI)
23PA12 [PA10]I/OMultiplexed I/O & Peripheral Pin PA12 [PA10] (UART, SPI, I2C)
24PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
25PA14BOOT0 -I/OMultiplexed I/O & Peripheral Pin PA14BOOT0 - (UART, SWD/JTAG)
26PA15I/OMultiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)
27PB3I/OMultiplexed I/O & Peripheral Pin PB3 (UART, SPI, PWM)
28PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, PWM)
29PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, PWM)
30PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART)
31PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART)
32PB8I/OMultiplexed I/O & Peripheral Pin PB8 (SPI)
33EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 PB9
I/O
Multiplexed I/O & Peripheral Pin PB9 (SPI)
Design note: Alt: IR_OUTUCPD2FRSTX ,_ , TIM17_CH1USART3RX ,_ , SPI2_NSSI2C1SDA ,_ , EVENTOUT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 19 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32G071KBU3TR (ST · UFQFPN-32(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32G071KBU3TR (UFQFPN-32(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32G071KBU3TR (UFQFPN-32(5x5)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32G071KBU3TR (UFQFPN-32(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32G071KBU3TR (UFQFPN-32(5x5)) - 4. Package Dimensions (D×E×A)
UFQFPN-32(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32G071KBU3TR (UFQFPN-32(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32G071KBU3TR (UFQFPN-32(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (19 figures · Page 1/2)
Showing 1–12 of 19 uncropped original figures for STM32G071
P1 · p01_fig01EXACT PACKAGE
STM32G071KBU3TR (UFQFPN-32(5x5)) — Arm® Cortex®-M0+ 32-bit MCU, up to 128 KB Flash, 36 KB RAM,
Arm® Cortex®-M0+ 32-bit MCU, up to 128 KB Flash, 36 KB RAM,
P1 · p01_fig02EXACT PACKAGE
STM32G071KBU3TR (UFQFPN-32(5x5)) — 5 × 5 mm
5 × 5 mm
P39 · p39_fig01EXACT PACKAGE
STM32G071KBU3TR (UFQFPN-32(5x5)) — Figure 8. STM32G071KxU UFQFPN32 pinout
Figure 8. STM32G071KxU UFQFPN32 pinout
P39 · p39_fig02EXACT PACKAGE
STM32G071KBU3TR (UFQFPN-32(5x5)) — Figure 8. STM32G071KxU UFQFPN32 pinout
Figure 8. STM32G071KxU UFQFPN32 pinout
P39 · p39_fig03EXACT PACKAGE
STM32G071KBU3TR (UFQFPN-32(5x5)) — PB0
PB0
P41 · p41_fig01EXACT PACKAGE
STM32G071KBU3TR (UFQFPN-32(5x5)) — DS12232 Rev 4 41/135
DS12232 Rev 4 41/135
P113 · p113_fig01EXACT PACKAGE
STM32G071KBU3TR (UFQFPN-32(5x5)) — Figure 38. UFQFPN32 package outline D
Figure 38. UFQFPN32 package outline D
P113 · p113_fig02EXACT PACKAGE
STM32G071KBU3TR (UFQFPN-32(5x5)) — 1. Drawing is not to scale.
1. Drawing is not to scale.
P114 · p114_fig01EXACT PACKAGE
STM32G071KBU3TR (UFQFPN-32(5x5)) — Figure 39. Recommended footprint for UFQFPN32 package
Figure 39. Recommended footprint for UFQFPN32 package
P114 · p114_fig02EXACT PACKAGE
STM32G071KBU3TR (UFQFPN-32(5x5)) — Figure 40. UFQFPN32 package marking example
Figure 40. UFQFPN32 package marking example
P1 · p01_fig02P1
STM32G071KBU3TR (UFQFPN-32(5x5)) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P53 · p53_fig011548×1316px
STM32G071KBU3TR (UFQFPN-32(5x5)) — Figure 13. Power supply scheme
Figure 13. Power supply scheme
Page 1 / 2 (19 extracted figures)

Technical Specifications & Part Details (STM32G071KBU3TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32G071KBU3TR (UFQFPN-32(5x5)) is a 32-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.62 V - 3.6 V supply operation across -40°C to 85°C with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.62 V - 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
64 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
28 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.60 mm (A1=0.04 mm)
Package family: QFN (UFQFPN-32(5x5))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PA14BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.50×3.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFQFPN-32(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 0.75 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFQFPN-32(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32G071KBU3TR (UFQFPN-32(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32G071KBU3TR (UFQFPN-32(5x5))?

Manufactured by ST, the STM32G071KBU3TR is housed in a UFQFPN-32(5x5) package with 33 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.62 V - 3.6 V. Key pins include: 1 (PB9: Multiplexed I/O & Peripheral Pin PB9 (SPI)), 2 (PC14 - OSC32_IN (PC14): Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (VDD/VDDA: Power Supply Input (VDD/VDDA — 3.3V VDD (Max 4.0V))), 5 (VSS/VSSA: Ground Reference Pin (VSS/VSSA)), 6 (PF2 NRST -: Multiplexed I/O & Peripheral Pin PF2 NRST - (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32G071KBU3TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32G071KBU3TR (UFQFPN-32(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.50 × 3.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32G071KBU3TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32G071KBU3TR (ST, UFQFPN-32(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & STM32G071 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSI2C1SDA. Supported peripheral buses: SPI.
2PC14 - OSC32_IN (PC14)Digital_IOSignal terminal PC14 - OSC32_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN (PC14). Supported peripheral buses: RTC/CLK.
33V3Power_In3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4VDD/VDDAPower_InPrimary positive power supply input (VDD/VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
5VSS/VSSAGND0V electrical ground return terminal (VSS/VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
6PF2 NRST -Digital_IOSignal terminal PF2 NRST - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF2 NRST -. Supported peripheral buses: RTC/CLK.
7PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKUSART2CTS. Supported peripheral buses: UART, SPI, PWM.
8PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, PWM.
9PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI.
10PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOUSART2RX. Supported peripheral buses: SPI, PWM.
11PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI2_MOSITIM14CH1. Supported peripheral buses: SPI, ADC, RTC/CLK.
12PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, ADC, PWM.
13PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC, PWM.
14PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
15PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, PWM.
16PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, PWM.
17PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOUSART3TX. Supported peripheral buses: SPI.
18PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI, PWM, RTC/CLK.
19PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, PWM, RTC/CLK.
20PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
21PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSIUSART1RX, I2C1_SDAEVENTOUT. Supported peripheral buses: SPI, I2C, PWM.
22PA11 [PA9]Digital_IOSignal terminal PA11 [PA9] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI.
23PA12 [PA10]Digital_IOSignal terminal PA12 [PA10] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI, I2C.
24PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
25PA14BOOT0 -Digital_IOSignal terminal PA14BOOT0 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14BOOT0 -. Supported peripheral buses: UART, SWD/JTAG.
26PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, PWM.
27PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, PWM.
28PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, PWM.
29PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, PWM.
30PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART.
31PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART.
32PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI.
33EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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