WFBGA-48(4x6) · 48P
48P4.0×6.0×1.35mmP=0.5mm
SST39WF400B (WFBGA-48(4x6))
Synchronized Pinout (Symbol / 2D / 3D) (48/48)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| A2 | VSS | GND | Ground Reference Pin (VSS) |
| A3 | CE# | I/O | Multiplexed I/O & Peripheral Pin CE# (General) |
| A4 | A0 | I/O | Multiplexed I/O & Peripheral Pin A0 (General) |
| A5 | A1 | I/O | Multiplexed I/O & Peripheral Pin A1 (General) |
| A6 | A2 | I/O | Multiplexed I/O & Peripheral Pin A2 (General) |
| B1 | DQ0 | I/O | Multiplexed I/O & Peripheral Pin DQ0 (General) |
| B2 | OE# | I/O | Multiplexed I/O & Peripheral Pin OE# (General) |
| B3 | DQ8 | I/O | Multiplexed I/O & Peripheral Pin DQ8 (General) |
| B4 | A5 | I/O | Multiplexed I/O & Peripheral Pin A5 (General) |
| B5 | A3 | I/O | Multiplexed I/O & Peripheral Pin A3 (General) |
| B6 | A4 | I/O | Multiplexed I/O & Peripheral Pin A4 (General) |
| C1 | DQ1 | I/O | Multiplexed I/O & Peripheral Pin DQ1 (General) |
| C2 | DQ9 | I/O | Multiplexed I/O & Peripheral Pin DQ9 (General) |
| C3 | DQ10 | I/O | Multiplexed I/O & Peripheral Pin DQ10 (General) |
| C4 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| C5 | A7 | I/O | Multiplexed I/O & Peripheral Pin A7 (General) |
| C6 | A6 | I/O | Multiplexed I/O & Peripheral Pin A6 (General) |
| D1 | DQ2 | I/O | Multiplexed I/O & Peripheral Pin DQ2 (General) |
| D2 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| D5 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| D6 | A17 | I/O | Multiplexed I/O & Peripheral Pin A17 (General) |
| E1 | DQ3 | I/O | Multiplexed I/O & Peripheral Pin DQ3 (General) |
| E6 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| F1 | VDD | Power | Power Supply Input (VDD — 3.3V / 5.0V Standard Logic) |
| F6 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| G1 | DQ12 | I/O | Multiplexed I/O & Peripheral Pin DQ12 (General) |
| G6 | WE# | I/O | Multiplexed I/O & Peripheral Pin WE# (General) |
| H1 | DQ13 | I/O | Multiplexed I/O & Peripheral Pin DQ13 (General) |
| H2 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| H5 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| H6 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| J1 | DQ14 | I/O | Multiplexed I/O & Peripheral Pin DQ14 (General) |
| J2 | DQ5 | I/O | Multiplexed I/O & Peripheral Pin DQ5 (General) |
| J3 | DQ4 | I/O | Multiplexed I/O & Peripheral Pin DQ4 (General) |
| J4 | A8 | I/O | Multiplexed I/O & Peripheral Pin A8 (General) |
| J5 | A10 | I/O | Multiplexed I/O & Peripheral Pin A10 (General) |
| J6 | A9 | I/O | Multiplexed I/O & Peripheral Pin A9 (General) |
| K1 | DQ15 | I/O | Multiplexed I/O & Peripheral Pin DQ15 (General) |
| K2 | DQ6 | I/O | Multiplexed I/O & Peripheral Pin DQ6 (General) |
| K3 | DQ11 | I/O | Multiplexed I/O & Peripheral Pin DQ11 (General) |
| K4 | A12 | I/O | Multiplexed I/O & Peripheral Pin A12 (General) |
| K5 | A13 | I/O | Multiplexed I/O & Peripheral Pin A13 (General) |
| K6 | A11 | I/O | Multiplexed I/O & Peripheral Pin A11 (General) |
| L1 | VSS | GND | Ground Reference Pin (VSS) |
| L2 | DQ7 | I/O | Multiplexed I/O & Peripheral Pin DQ7 (General) |
| L3 | A16 | I/O | Multiplexed I/O & Peripheral Pin A16 (General) |
| L4 | A15 | I/O | Multiplexed I/O & Peripheral Pin A15 (General) |
| L5 | A14 | I/O | Multiplexed I/O & Peripheral Pin A14 (General) |
PIN A2 VSS
GNDGround Reference Pin (VSS)
Design note: 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
WFBGA-48(4x6) · 6.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for SST39WF400B
P1 · p01_fig01469×310px
P2 · p02_fig01468×310px
P4 · p04_fig01468×310px
P4 · p04_fig022040×1466px
P4 · p04_fig02P4
P5 · p05_fig01468×310px
P30 · p30_fig012040×1573px
P31 · p31_fig012040×1684px
P31 · p31_fig01P31
P32 · p32_fig01468×310px
Technical Specifications & Part Details (SST39WF400B-70-4C-MAQE-T)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:SST39WF400B-70-4C-MAQE-T (WFBGA-48(4x6)) is a 48-pin standard electronic & interconnect component featuring a 4.00 × 6.00 × 1.35 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
5 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 6.00 × 1.35 mm (A1=0.30 mm)
Package family: BGA (WFBGA-48(4x6))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol48 auto-grouped pins
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — SST39WF400B (3)
WFBGA-48(4x6) · 48P
48P4.0×6.0×1.35mmP=0.5mm
SST39WF400B (WFBGA-48(4x6))
WFBGA-48(4x6) · 48P
48P4.0×6.0×1.35mmP=0.5mm
SST39WF400B (WFBGA-48(4x6))
Mechanical Dimensions & Land Pattern (WFBGA-48(4x6))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
4.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.35mm · e=0.50mm
Pad Size (W × L)Level B
0.26 × 0.26 mm
Pins / Total PadsTopology
48P / 48Pad (BGA_GRID)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit WFBGA-48(4x6) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — SST39WF400B-70-4C-MAQE-T (WFBGA-48(4x6))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of SST39WF400B-70-4C-MAQE-T (WFBGA-48(4x6))?
Manufactured by MICROCHIP, the SST39WF400B-70-4C-MAQE-T is housed in a WFBGA-48(4x6) package with 48 pins and a 0.50 mm lead pitch. Key pins include: A2 (VSS: Ground Reference Pin (VSS)), A3 (CE#: Multiplexed I/O & Peripheral Pin CE# (General)), A4 (A0: Multiplexed I/O & Peripheral Pin A0 (General)), A5 (A1: Multiplexed I/O & Peripheral Pin A1 (General)), A6 (A2: Multiplexed I/O & Peripheral Pin A2 (General)), B1 (DQ0: Multiplexed I/O & Peripheral Pin DQ0 (General)).
What are the IPC-7351B PCB Footprint dimensions for SST39WF400B-70-4C-MAQE-T?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SST39WF400B-70-4C-MAQE-T (WFBGA-48(4x6)) has a nominal body envelope of 6.00 × 4.00 mm, pitch e = 0.50 mm, and 48 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for SST39WF400B-70-4C-MAQE-T?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SST39WF400B-70-4C-MAQE-T (MICROCHIP, WFBGA-48(4x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (48 pins) & SST39WF400B Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| A2 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| A3 | CE# | Digital_IO | Signal terminal CE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CE#. Supported peripheral buses: General. |
| A4 | A0 | Digital_IO | Signal terminal A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0. Supported peripheral buses: General. |
| A5 | A1 | Digital_IO | Signal terminal A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1. Supported peripheral buses: General. |
| A6 | A2 | Digital_IO | Signal terminal A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2. Supported peripheral buses: General. |
| B1 | DQ0 | Digital_IO | Signal terminal DQ0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ0. Supported peripheral buses: General. |
| B2 | OE# | Digital_IO | Signal terminal OE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OE#. Supported peripheral buses: General. |
| B3 | DQ8 | Digital_IO | Signal terminal DQ8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ8. Supported peripheral buses: General. |
| B4 | A5 | Digital_IO | Signal terminal A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A5. Supported peripheral buses: General. |
| B5 | A3 | Digital_IO | Signal terminal A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3. Supported peripheral buses: General. |
| B6 | A4 | Digital_IO | Signal terminal A4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A4. Supported peripheral buses: General. |
| C1 | DQ1 | Digital_IO | Signal terminal DQ1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ1. Supported peripheral buses: General. |
| C2 | DQ9 | Digital_IO | Signal terminal DQ9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ9. Supported peripheral buses: General. |
| C3 | DQ10 | Digital_IO | Signal terminal DQ10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ10. Supported peripheral buses: General. |
| C4 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| C5 | A7 | Digital_IO | Signal terminal A7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A7. Supported peripheral buses: General. |
| C6 | A6 | Digital_IO | Signal terminal A6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A6. Supported peripheral buses: General. |
| D1 | DQ2 | Digital_IO | Signal terminal DQ2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ2. Supported peripheral buses: General. |
| D2 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| D5 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| D6 | A17 | Digital_IO | Signal terminal A17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A17. Supported peripheral buses: General. |
| E1 | DQ3 | Digital_IO | Signal terminal DQ3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ3. Supported peripheral buses: General. |
| E6 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| F1 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| F6 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| G1 | DQ12 | Digital_IO | Signal terminal DQ12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ12. Supported peripheral buses: General. |
| G6 | WE# | Digital_IO | Signal terminal WE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WE#. Supported peripheral buses: General. |
| H1 | DQ13 | Digital_IO | Signal terminal DQ13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ13. Supported peripheral buses: General. |
| H2 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| H5 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| H6 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| J1 | DQ14 | Digital_IO | Signal terminal DQ14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ14. Supported peripheral buses: General. |
| J2 | DQ5 | Digital_IO | Signal terminal DQ5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ5. Supported peripheral buses: General. |
| J3 | DQ4 | Digital_IO | Signal terminal DQ4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ4. Supported peripheral buses: General. |
| J4 | A8 | Digital_IO | Signal terminal A8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A8. Supported peripheral buses: General. |
| J5 | A10 | Digital_IO | Signal terminal A10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A10. Supported peripheral buses: General. |
| J6 | A9 | Digital_IO | Signal terminal A9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A9. Supported peripheral buses: General. |
| K1 | DQ15 | Digital_IO | Signal terminal DQ15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ15. Supported peripheral buses: General. |
| K2 | DQ6 | Digital_IO | Signal terminal DQ6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ6. Supported peripheral buses: General. |
| K3 | DQ11 | Digital_IO | Signal terminal DQ11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ11. Supported peripheral buses: General. |
| K4 | A12 | Digital_IO | Signal terminal A12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A12. Supported peripheral buses: General. |
| K5 | A13 | Digital_IO | Signal terminal A13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A13. Supported peripheral buses: General. |
| K6 | A11 | Digital_IO | Signal terminal A11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A11. Supported peripheral buses: General. |
| L1 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| L2 | DQ7 | Digital_IO | Signal terminal DQ7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ7. Supported peripheral buses: General. |
| L3 | A16 | Digital_IO | Signal terminal A16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A16. Supported peripheral buses: General. |
| L4 | A15 | Digital_IO | Signal terminal A15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A15. Supported peripheral buses: General. |
| L5 | A14 | Digital_IO | Signal terminal A14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A14. Supported peripheral buses: General. |