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SCH3223-7U-TR (WFBGA-64) — Symbol, Footprint IPC-7351B & 3D STEP Model

SCH3223-7U-TR

MICROCHIPID: C626302WFBGA-64 · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · SCH3223-7U-TR (WFBGA-64)A2+25V IN ._A3REMOTE1+A5PWM1A7nFPRST / GP3A9nRSMRSTA10GP63B1+12V_INB2VCCP_INB3REMOTE1 -B4HVTRB5FANTACH1B7PWRGD_PSB8PWRGD_OUTB9GP62B10CLKI32B11GP60 / nLED1C1+5V_INC2VTRC10GP61 / nLED2C11GP42 / nIO_PD2TEST VSS =D5HVSSD6GP57 / nDTR2D7PB OUT#_D10SLP SX#_E1CLOCKIE2VSSE4LAD0E8GP56 / nCTS2E10PS ON#_E11PB IN#_F4LAD1L10nDCD1L9nRI1L7VSSL5VTRL3AVSSL2nPCIRST3 / GK11RXD1K10nCTS1K9nRTS1 / SYSOK8nDSR1K7TXD1K5GP27 / nIO_SK4VBATK3VCCK2nPCIRST1 / GK1nPCIRST2 / GJ11GP50 / nRI2J10nDTR1 / SYSOJ2VSSJ1nIDE RSTDRV H10VTRH7GP51 / nDCD2H6PCI RESET#_H5PCI_CLKH2SER_IRQG11GP52 / RXD2G10GP53 / TXD2G8GP54 / nDSR2G4LAD2G2LAD3G1LFRAME#F8GP55 / nRTS2Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
B1C1E1G1J1K1A2B2C2D2E2G2H2J2K2L2A3B3K3L3B4E4F4G4K4A5B5D5H5K5L5D6H6A7B7D7H7K7L7B8E8F8G8K8A9B9K9L9A10B10C10D10E10G10H10J10K10L10B11C11E11G11J11K11E=6.00mm · Pitch e=0.50mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A2+25V IN ._PowerPower Supply Input (+25V IN ._ — 3.3V / 5.0V Standard Logic)
A3REMOTE1+I/OMultiplexed I/O & Peripheral Pin REMOTE1+ (General)
A5PWM1I/OMultiplexed I/O & Peripheral Pin PWM1 (PWM)
A7nFPRST / GP30I/OMultiplexed I/O & Peripheral Pin nFPRST / GP30 (General)
A9nRSMRSTI/OMultiplexed I/O & Peripheral Pin nRSMRST (General)
A10GP63I/OMultiplexed I/O & Peripheral Pin GP63 (General)
B1+12V_INI/OMultiplexed I/O & Peripheral Pin +12V_IN (General)
B2VCCP_INPowerPower Supply Input (VCCP_IN — 3.3V / 5.0V Standard Logic)
B3REMOTE1 -I/OMultiplexed I/O & Peripheral Pin REMOTE1 - (General)
B4HVTRI/OMultiplexed I/O & Peripheral Pin HVTR (General)
B5FANTACH1I/OMultiplexed I/O & Peripheral Pin FANTACH1 (General)
B7PWRGD_PSI/OMultiplexed I/O & Peripheral Pin PWRGD_PS (General)
B8PWRGD_OUTI/OMultiplexed I/O & Peripheral Pin PWRGD_OUT (General)
B9GP62I/OMultiplexed I/O & Peripheral Pin GP62 (General)
B10CLKI32I/OMultiplexed I/O & Peripheral Pin CLKI32 (General)
B11GP60 / nLED1 / WDTI/OMultiplexed I/O & Peripheral Pin GP60 / nLED1 / WDT (General)
C1+5V_INPowerPower Supply Input (+5V_IN — 3.3V / 5.0V Standard Logic)
C2VTRI/OMultiplexed I/O & Peripheral Pin VTR (General)
C10GP61 / nLED2 / CLKOI/OMultiplexed I/O & Peripheral Pin GP61 / nLED2 / CLKO (General)
C11GP42 / nIO_PMEI/OMultiplexed I/O & Peripheral Pin GP42 / nIO_PME (General)
D2TEST VSS =GNDGround Reference Pin (TEST VSS =)
D5HVSSGNDGround Reference Pin (HVSS)
D6GP57 / nDTR2I/OMultiplexed I/O & Peripheral Pin GP57 / nDTR2 (General)
D7PB OUT#_I/OMultiplexed I/O & Peripheral Pin PB OUT#_ (General)
D10SLP SX#_I/OMultiplexed I/O & Peripheral Pin SLP SX#_ (General)
E1CLOCKII/OMultiplexed I/O & Peripheral Pin CLOCKI (General)
E2VSSGNDGround Reference Pin (VSS)
E4LAD0I/OMultiplexed I/O & Peripheral Pin LAD0 (General)
E8GP56 / nCTS2I/OMultiplexed I/O & Peripheral Pin GP56 / nCTS2 (General)
E10PS ON#_I/OMultiplexed I/O & Peripheral Pin PS ON#_ (General)
E11PB IN#_I/OMultiplexed I/O & Peripheral Pin PB IN#_ (General)
F4LAD1I/OMultiplexed I/O & Peripheral Pin LAD1 (General)
F8GP55 / nRTS2 / RESGENI/OMultiplexed I/O & Peripheral Pin GP55 / nRTS2 / RESGEN (General)
G1LFRAME#I/OMultiplexed I/O & Peripheral Pin LFRAME# (General)
G2LAD3I/OMultiplexed I/O & Peripheral Pin LAD3 (General)
G4LAD2I/OMultiplexed I/O & Peripheral Pin LAD2 (General)
G8GP54 / nDSR2I/OMultiplexed I/O & Peripheral Pin GP54 / nDSR2 (General)
G10GP53 / TXD2I/OMultiplexed I/O & Peripheral Pin GP53 / TXD2 (UART)
G11GP52 / RXD2I/OMultiplexed I/O & Peripheral Pin GP52 / RXD2 (UART)
H2SER_IRQI/OMultiplexed I/O & Peripheral Pin SER_IRQ (General)
H5PCI_CLKI/OMultiplexed I/O & Peripheral Pin PCI_CLK (General)
H6PCI RESET#_ISystem Enable & Hardware Reset (PCI RESET#_)
H7GP51 / nDCD2I/OMultiplexed I/O & Peripheral Pin GP51 / nDCD2 (General)
H10VTRI/OMultiplexed I/O & Peripheral Pin VTR (General)
J1nIDE RSTDRV / GP44_I/OMultiplexed I/O & Peripheral Pin nIDE RSTDRV / GP44_ (General)
J2VSSGNDGround Reference Pin (VSS)
J10nDTR1 / SYSOPT1I/OMultiplexed I/O & Peripheral Pin nDTR1 / SYSOPT1 (General)
J11GP50 / nRI2I/OMultiplexed I/O & Peripheral Pin GP50 / nRI2 (General)
K1nPCIRST2 / GP46I/OMultiplexed I/O & Peripheral Pin nPCIRST2 / GP46 (General)
K2nPCIRST1 / GP45I/OMultiplexed I/O & Peripheral Pin nPCIRST1 / GP45 (General)
K3VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
K4VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
K5GP27 / nIO_SMII/OMultiplexed I/O & Peripheral Pin GP27 / nIO_SMI (General)
K7TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
K8nDSR1I/OMultiplexed I/O & Peripheral Pin nDSR1 (General)
K9nRTS1 / SYSOPT0I/OMultiplexed I/O & Peripheral Pin nRTS1 / SYSOPT0 (General)
K10nCTS1I/OMultiplexed I/O & Peripheral Pin nCTS1 (General)
K11RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
L2nPCIRST3 / GP47I/OMultiplexed I/O & Peripheral Pin nPCIRST3 / GP47 (General)
L3AVSSGNDGround Reference Pin (AVSS)
L5VTRI/OMultiplexed I/O & Peripheral Pin VTR (General)
L7VSSGNDGround Reference Pin (VSS)
L9nRI1I/OMultiplexed I/O & Peripheral Pin nRI1 (General)
L10nDCD1I/OMultiplexed I/O & Peripheral Pin nDCD1 (General)
PIN A2 +25V IN ._
Power
Power Supply Input (+25V IN ._ — 3.3V / 5.0V Standard Logic)
Design note: +25V IN ._
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: SCH3223-7U-TR (MICROCHIP · WFBGA-64)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
SCH3223-7U-TR (WFBGA-64) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
SCH3223-7U-TR (WFBGA-64) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
SCH3223-7U-TR (WFBGA-64) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SCH3223-7U-TR (WFBGA-64) - 4. Package Dimensions (D×E×A)
WFBGA-64 · 6.00×6.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
SCH3223-7U-TR (WFBGA-64) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
SCH3223-7U-TR (WFBGA-64) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for SCH3223
P1 · p01_fig01377×200px
SCH3223-7U-TR (WFBGA-64) — LPC IO with Reset Generation, HWM and
LPC IO with Reset Generation, HWM and
P5 · p05_fig011650×1453px
SCH3223-7U-TR (WFBGA-64) — FIGURE 2-1: SCH3223 64-BALL WFBGA FOOTPRINT DIAGRAM, TOP VIEW
FIGURE 2-1: SCH3223 64-BALL WFBGA FOOTPRINT DIAGRAM, TOP VIEW
P5 · p05_fig01P5
SCH3223-7U-TR (WFBGA-64) — Datasheet Page 5 (p05_fig01)
Datasheet Page 5 (p05_fig01)
P6 · p06_fig011778×2734px
SCH3223-7U-TR (WFBGA-64) — SCH3223 | DS00002028B-page 6  2015 Microchip Technology Inc. | 2.1 SCH3223 Pin Layout Summary | TABLE 2-1: SCH3223 SUMMARY | Ball# Function (Note 1) | B1 +12V_IN | C1 +5V_IN | C2 VTR | D2 TEST=VSS | E2 VSS | E1 CLOCKI | E4 LAD0 | F4 LAD1 |
SCH3223 | DS00002028B-page 6  2015 Microchip Technology Inc. | 2.1 SCH3223 Pin Layout Summary | TABLE 2-1: SCH3223 SUMMARY | Ball# Function (Note 1) | B1 +12V_IN | C1 +5V_IN | C2 VTR | D2 TEST=VSS | E2 VSS | E1 CLOCKI | E4 LAD0 | F4 LAD1 |
P6 · p06_fig01P6
SCH3223-7U-TR (WFBGA-64) — Datasheet Page 6 (p06_fig01)
Datasheet Page 6 (p06_fig01)
P35 · p35_fig011782×1503px
SCH3223-7U-TR (WFBGA-64) — FIGURE 7-3: HALF DUPLEX OPERATION WITH DIRECTION CONTROL
FIGURE 7-3: HALF DUPLEX OPERATION WITH DIRECTION CONTROL
P188 · p188_fig011777×2329px
SCH3223-7U-TR (WFBGA-64) — FIGURE 27-1: 64-Ball WFBGA Package Outline; 6x6 mm Body, 0.5mm Pitch (0.65 compatible)
FIGURE 27-1: 64-Ball WFBGA Package Outline; 6x6 mm Body, 0.5mm Pitch (0.65 compatible)
P188 · p188_fig02144×361px
SCH3223-7U-TR (WFBGA-64) — ;
;

Technical Specifications & Part Details (SCH3223-7U-TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:SCH3223-7U-TR (WFBGA-64) is a 64-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.35 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, ADC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
19MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 1.35 mm (A1=0.30 mm)
Package family: BGA (WFBGA-64)
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, ADC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WFBGA-64)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.35mm · e=0.50mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
64P / 64Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WFBGA-64
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — SCH3223-7U-TR (WFBGA-64)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of SCH3223-7U-TR (WFBGA-64)?

Manufactured by MICROCHIP, the SCH3223-7U-TR is housed in a WFBGA-64 package with 64 pins and a 0.50 mm lead pitch. Key pins include: A2 (+25V IN ._: Power Supply Input (+25V IN ._ — 3.3V / 5.0V Standard Logic)), A3 (REMOTE1+: Multiplexed I/O & Peripheral Pin REMOTE1+ (General)), A5 (PWM1: Multiplexed I/O & Peripheral Pin PWM1 (PWM)), A7 (nFPRST / GP30: Multiplexed I/O & Peripheral Pin nFPRST / GP30 (General)), A9 (nRSMRST: Multiplexed I/O & Peripheral Pin nRSMRST (General)), A10 (GP63: Multiplexed I/O & Peripheral Pin GP63 (General)).

What are the IPC-7351B PCB Footprint dimensions for SCH3223-7U-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SCH3223-7U-TR (WFBGA-64) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for SCH3223-7U-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SCH3223-7U-TR (MICROCHIP, WFBGA-64) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & SCH3223 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A2+25V IN ._Power_InPrimary positive power supply input (+25V IN ._) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
A3REMOTE1+Digital_IOSignal terminal REMOTE1+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: REMOTE1+. Supported peripheral buses: General.
A5PWM1Digital_IOSignal terminal PWM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM1. Supported peripheral buses: PWM.
A7nFPRST / GP30Digital_IOSignal terminal nFPRST / GP30 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nFPRST / GP30. Supported peripheral buses: General.
A9nRSMRSTDigital_IOSignal terminal nRSMRST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nRSMRST. Supported peripheral buses: General.
A10GP63Digital_IOSignal terminal GP63 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP63. Supported peripheral buses: General.
B1+12V_INDigital_IOSignal terminal +12V_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: +12V_IN. Supported peripheral buses: General.
B2VCCP_INPower_InPrimary positive power supply input (VCCP_IN) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
B3REMOTE1 -Digital_IOSignal terminal REMOTE1 - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: REMOTE1 -. Supported peripheral buses: General.
B4HVTRDigital_IOSignal terminal HVTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVTR. Supported peripheral buses: General.
B5FANTACH1RF_50OhmSignal terminal FANTACH1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FANTACH1. Supported peripheral buses: General.
B7PWRGD_PSDigital_IOSignal terminal PWRGD_PS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWRGD_PS. Supported peripheral buses: General.
B8PWRGD_OUTDigital_IOSignal terminal PWRGD_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWRGD_OUT. Supported peripheral buses: General.
B9GP62Digital_IOSignal terminal GP62 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP62. Supported peripheral buses: General.
B10CLKI32Digital_IOSignal terminal CLKI32 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLKI32. Supported peripheral buses: General.
B11GP60 / nLED1 / WDTDigital_IOSignal terminal GP60 / nLED1 / WDT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP60 / nLED1 / WDT. Supported peripheral buses: General.
C1+5V_INPower_InPrimary positive power supply input (+5V_IN) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
C2VTRDigital_IOSignal terminal VTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR. Supported peripheral buses: General.
C10GP61 / nLED2 / CLKODigital_IOSignal terminal GP61 / nLED2 / CLKO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP61 / nLED2 / CLKO. Supported peripheral buses: General.
C11GP42 / nIO_PMEDigital_IOSignal terminal GP42 / nIO_PME (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP42 / nIO_PME. Supported peripheral buses: General.
D2TEST VSS =GND0V electrical ground return terminal (TEST VSS =) for internal core logic, I/O drivers, and analog sub-blocks.
D5HVSSGND0V electrical ground return terminal (HVSS) for internal core logic, I/O drivers, and analog sub-blocks.
D6GP57 / nDTR2Digital_IOSignal terminal GP57 / nDTR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP57 / nDTR2. Supported peripheral buses: General.
D7PB OUT#_Digital_IOSignal terminal PB OUT#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB OUT#_. Supported peripheral buses: General.
D10SLP SX#_Digital_IOSignal terminal SLP SX#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SLP SX#_. Supported peripheral buses: General.
E1CLOCKIDigital_IOSignal terminal CLOCKI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLOCKI. Supported peripheral buses: General.
E2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E4LAD0Digital_IOSignal terminal LAD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD0. Supported peripheral buses: General.
E8GP56 / nCTS2Digital_IOSignal terminal GP56 / nCTS2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP56 / nCTS2. Supported peripheral buses: General.
E10PS ON#_Digital_IOSignal terminal PS ON#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PS ON#_. Supported peripheral buses: General.
E11PB IN#_Digital_IOSignal terminal PB IN#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB IN#_. Supported peripheral buses: General.
F4LAD1Digital_IOSignal terminal LAD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD1. Supported peripheral buses: General.
F8GP55 / nRTS2 / RESGENDigital_IOSignal terminal GP55 / nRTS2 / RESGEN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP55 / nRTS2 / RESGEN. Supported peripheral buses: General.
G1LFRAME#Digital_IOSignal terminal LFRAME# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LFRAME#. Supported peripheral buses: General.
G2LAD3Digital_IOSignal terminal LAD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD3. Supported peripheral buses: General.
G4LAD2Digital_IOSignal terminal LAD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD2. Supported peripheral buses: General.
G8GP54 / nDSR2Digital_IOSignal terminal GP54 / nDSR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP54 / nDSR2. Supported peripheral buses: General.
G10GP53 / TXD2Digital_IOSignal terminal GP53 / TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP53 / TXD2. Supported peripheral buses: UART.
G11GP52 / RXD2Digital_IOSignal terminal GP52 / RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP52 / RXD2. Supported peripheral buses: UART.
H2SER_IRQDigital_IOSignal terminal SER_IRQ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SER_IRQ. Supported peripheral buses: General.
H5PCI_CLKDigital_IOSignal terminal PCI_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PCI_CLK. Supported peripheral buses: General.
H6PCI RESET#_Digital_IOActive-low hardware reset terminal (PCI RESET#_): pulling this pin Low resets the processor core and peripherals.
H7GP51 / nDCD2Digital_IOSignal terminal GP51 / nDCD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP51 / nDCD2. Supported peripheral buses: General.
H10VTRDigital_IOSignal terminal VTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR. Supported peripheral buses: General.
J1nIDE RSTDRV / GP44_Digital_IOSignal terminal nIDE RSTDRV / GP44_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nIDE RSTDRV / GP44_. Supported peripheral buses: General.
J2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
J10nDTR1 / SYSOPT1Digital_IOSignal terminal nDTR1 / SYSOPT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nDTR1 / SYSOPT1. Supported peripheral buses: General.
J11GP50 / nRI2Digital_IOSignal terminal GP50 / nRI2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP50 / nRI2. Supported peripheral buses: General.
K1nPCIRST2 / GP46Digital_IOSignal terminal nPCIRST2 / GP46 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nPCIRST2 / GP46. Supported peripheral buses: General.
K2nPCIRST1 / GP45Digital_IOSignal terminal nPCIRST1 / GP45 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nPCIRST1 / GP45. Supported peripheral buses: General.
K3VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
K4VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
K5GP27 / nIO_SMIDigital_IOSignal terminal GP27 / nIO_SMI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP27 / nIO_SMI. Supported peripheral buses: General.
K7TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
K8nDSR1Digital_IOSignal terminal nDSR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nDSR1. Supported peripheral buses: General.
K9nRTS1 / SYSOPT0Digital_IOSignal terminal nRTS1 / SYSOPT0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nRTS1 / SYSOPT0. Supported peripheral buses: General.
K10nCTS1Digital_IOSignal terminal nCTS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nCTS1. Supported peripheral buses: General.
K11RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
L2nPCIRST3 / GP47Digital_IOSignal terminal nPCIRST3 / GP47 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nPCIRST3 / GP47. Supported peripheral buses: General.
L3AVSSGND0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
L5VTRDigital_IOSignal terminal VTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR. Supported peripheral buses: General.
L7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
L9nRI1Digital_IOSignal terminal nRI1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nRI1. Supported peripheral buses: General.
L10nDCD1Digital_IOSignal terminal nDCD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nDCD1. Supported peripheral buses: General.
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