Mechanical Dimensions & Land Pattern (ESSOP-10-150mil-1mm)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit ESSOP-10-150mil-1mm | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH343K (ESSOP-10-150mil-1mm)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH343K (ESSOP-10-150mil-1mm)?
Manufactured by WCH, the CH343K is housed in a ESSOP-10-150mil-1mm package with 11 pins and a 1.00 mm lead pitch, supporting a VCC supply range of 3.3V to 5V. Key pins include: 1 (VIO: Multiplexed I/O & Peripheral Pin VIO (General)), 2 (GND: Ground Reference Pin (GND)), 3 (VDD5: Power Supply Input (VDD5 — 3.3V to 5V)), 4 (TXD: Multiplexed I/O & Peripheral Pin TXD (UART)), 5 (RXD: Multiplexed I/O & Peripheral Pin RXD (UART)), 6 (V3: Regulated Power Output (V3 — 3.3V to 5V)).
What are the IPC-7351B PCB Footprint dimensions for CH343K?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH343K (ESSOP-10-150mil-1mm) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.00 mm, and 11 copper pads plus a central exposed thermal pad (EPAD) of 2.30 × 3.00 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH343K?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH343K (WCH, ESSOP-10-150mil-1mm) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (11 pins) & CH343 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VIO | Digital_IO | Signal terminal VIO (I/O, 3.3V to 5V domain). Multiplexed alternate functions: VIO. Supported peripheral buses: General. |
| 2 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 3 | VDD5 | Power_In | Primary positive power supply input (VDD5) operating in the 3.3V to 5V domain (Max rating: 5.0V). |
| 4 | TXD | Digital_IO | Signal terminal TXD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART. |
| 5 | RXD | Digital_IO | Signal terminal RXD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART. |
| 6 | V3 | Power_Out | Regulated power output rail (V3) operating in the 3.3V to 5V domain (Max rating: 5.0V). |
| 7 | UD+ | Digital_IO | Signal terminal UD+ (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB. |
| 8 | UD - | Digital_IO | Signal terminal UD - (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD -. Supported peripheral buses: USB. |
| 9 | VBUS | Power_In | Primary positive power supply input (VBUS) operating in the 3.3V to 5V domain (Max rating: 5.0V). |
| 10 | ACT# | Digital_IO | Signal terminal ACT# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: ACT#. Supported peripheral buses: USB. |
| 11 | DCD | Digital_IO | Signal terminal DCD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: DCD. Supported peripheral buses: UART. |