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CH334P (QFN-16(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH334P

WCHID: C5373042QFN-16(3x3) · 17 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH334P (QFN-16(3x3))1LED1 PSELF2PWREN2# PWRE3LED2 PGANG4PWREN# PWREN5SUSP PWREN4#6DM17DP18DM29DP217RESET# CDP16DP415DM414DP313DM312XO11XI10PWREN3# PWREGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617E=3.00mm · Pitch e=0.50mmD=3.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (17/17)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1LED1 PSELFI/OMultiplexed I/O & Peripheral Pin LED1 PSELF (General)
2PWREN2# PWREN2I/OMultiplexed I/O & Peripheral Pin PWREN2# PWREN2 (General)
3LED2 PGANGI/OMultiplexed I/O & Peripheral Pin LED2 PGANG (General)
4PWREN# PWREN1# PWREN1I/OMultiplexed I/O & Peripheral Pin PWREN# PWREN1# PWREN1 (General)
5SUSP PWREN4# PWREN4I/OMultiplexed I/O & Peripheral Pin SUSP PWREN4# PWREN4 (General)
6DM1I/OMultiplexed I/O & Peripheral Pin DM1 (General)
7DP1I/OMultiplexed I/O & Peripheral Pin DP1 (General)
8DM2I/OMultiplexed I/O & Peripheral Pin DM2 (General)
9DP2I/OMultiplexed I/O & Peripheral Pin DP2 (General)
10PWREN3# PWREN3I/OMultiplexed I/O & Peripheral Pin PWREN3# PWREN3 (General)
11XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
12XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
13DM3I/OMultiplexed I/O & Peripheral Pin DM3 (General)
14DP3I/OMultiplexed I/O & Peripheral Pin DP3 (General)
15DM4I/OMultiplexed I/O & Peripheral Pin DM4 (General)
16DP4I/OMultiplexed I/O & Peripheral Pin DP4 (General)
17RESET# CDPISystem Enable & Hardware Reset (RESET# CDP)
PIN 1 LED1 PSELF
I/O
Multiplexed I/O & Peripheral Pin LED1 PSELF (General)
Design note: Signal terminal LED1 PSELF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED1 PSELF. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH334P (WCH · QFN-16(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH334P (QFN-16(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH334P (QFN-16(3x3)) - 2. Standard Pinout (Top View)
True package pinout (17 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH334P (QFN-16(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH334P (QFN-16(3x3)) - 4. Package Dimensions (D×E×A)
QFN-16(3x3) · 3.00×3.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH334P (QFN-16(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (17 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH334P (QFN-16(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for CH334 / CH335
P1 · p01_fig01308×165px
CH334P (QFN-16(3x3)) — 概述
概述
P2 · p02_fig011818×2376px
CH334P (QFN-16(3x3)) — 图1-1 引脚分布
图1-1 引脚分布
P2 · p02_fig01P2
CH334P (QFN-16(3x3)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P8 · p08_fig011746×1773px
CH334P (QFN-16(3x3)) — 图3-1-3 持整控独检模 流检测。
图3-1-3 持整控独检模 流检测。
P8 · p08_fig01P8
CH334P (QFN-16(3x3)) — Datasheet Page 8 (p08_fig01)
Datasheet Page 8 (p08_fig01)
P11 · p11_fig011747×519px
CH334P (QFN-16(3x3)) — 图3-2-2 MC
图3-2-2 MC
P12 · p12_fig011746×1307px
CH334P (QFN-16(3x3)) — 引脚的下降沿对C42 放电，之后R42/C
引脚的下降沿对C42 放电，之后R42/C
P12 · p12_fig021746×937px
CH334P (QFN-16(3x3)) — 图3-3-2A 定
图3-3-2A 定
P26 · p26_fig011762×2211px
CH334P (QFN-16(3x3)) — 工业级应用建议将V5 和VDD33 都接
工业级应用建议将V5 和VDD33 都接
P27 · p27_fig011746×2206px
CH334P (QFN-16(3x3)) — 6.3 简化应用，可外部供电
6.3 简化应用，可外部供电

Technical Specifications & Part Details (CH334P)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH334P (QFN-16(3x3)) is a 16-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, I2C, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-16(3x3))
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, I2C, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol17 auto-grouped pins
OK
IPC-7351B Land Pattern17 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 1.70×1.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-16(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.75 mm
Pins / Total PadsTopology
17P / 17Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-16(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH334P (QFN-16(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH334P (QFN-16(3x3))?

Manufactured by WCH, the CH334P is housed in a QFN-16(3x3) package with 17 pins and a 0.50 mm lead pitch. Key pins include: 1 (LED1 PSELF: Multiplexed I/O & Peripheral Pin LED1 PSELF (General)), 2 (PWREN2# PWREN2: Multiplexed I/O & Peripheral Pin PWREN2# PWREN2 (General)), 3 (LED2 PGANG: Multiplexed I/O & Peripheral Pin LED2 PGANG (General)), 4 (PWREN# PWREN1# PWREN1: Multiplexed I/O & Peripheral Pin PWREN# PWREN1# PWREN1 (General)), 5 (SUSP PWREN4# PWREN4: Multiplexed I/O & Peripheral Pin SUSP PWREN4# PWREN4 (General)), 6 (DM1: Multiplexed I/O & Peripheral Pin DM1 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH334P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH334P (QFN-16(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 17 copper pads plus a central exposed thermal pad (EPAD) of 1.70 × 1.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH334P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH334P (WCH, QFN-16(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (17 pins) & CH334 / CH335 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1LED1 PSELFDigital_IOSignal terminal LED1 PSELF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED1 PSELF. Supported peripheral buses: General.
2PWREN2# PWREN2Digital_IOSignal terminal PWREN2# PWREN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN2# PWREN2. Supported peripheral buses: General.
3LED2 PGANGDigital_IOSignal terminal LED2 PGANG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED2 PGANG. Supported peripheral buses: General.
4PWREN# PWREN1# PWREN1Digital_IOSignal terminal PWREN# PWREN1# PWREN1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN# PWREN1# PWREN1. Supported peripheral buses: General.
5SUSP PWREN4# PWREN4Digital_IOSignal terminal SUSP PWREN4# PWREN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SUSP PWREN4# PWREN4. Supported peripheral buses: General.
6DM1Digital_IOSignal terminal DM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM1. Supported peripheral buses: General.
7DP1Digital_IOSignal terminal DP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP1. Supported peripheral buses: General.
8DM2Digital_IOSignal terminal DM2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM2. Supported peripheral buses: General.
9DP2Digital_IOSignal terminal DP2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP2. Supported peripheral buses: General.
10PWREN3# PWREN3Digital_IOSignal terminal PWREN3# PWREN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN3# PWREN3. Supported peripheral buses: General.
11XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
12XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
13DM3Digital_IOSignal terminal DM3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM3. Supported peripheral buses: General.
14DP3Digital_IOSignal terminal DP3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP3. Supported peripheral buses: General.
15DM4Digital_IOSignal terminal DM4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM4. Supported peripheral buses: General.
16DP4Digital_IOSignal terminal DP4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP4. Supported peripheral buses: General.
17RESET# CDPDigital_IOActive-low hardware reset terminal (RESET# CDP): pulling this pin Low resets the processor core and peripherals.
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