![STM32F730Z8T6 (LQFP-144(20x20)) — Figure 13. STM32F730R8 LQFP64 pinout [LQFP-64(10x10)]](/api/v1/assets/C478453/extracted/figures/p50_fig01.png)
![STM32F730Z8T6 (LQFP-144(20x20)) — Figure 71. LQFP64 - 10 x 10 mm, low-profile quad flat package outline SEATING PLANE C A [LQFP-64(10x10)]](/api/v1/assets/C478453/extracted/figures/p185_fig01.png)
LQFP-64(10x10) · 64P
Synchronized Pinout (Symbol / 2D / 3D) (144/144)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | PE2 | I/O | Multiplexed I/O & Peripheral Pin PE2 (SPI) |
| 2 | PE3 | I/O | Multiplexed I/O & Peripheral Pin PE3 (General) |
| 3 | PE4 | I/O | Multiplexed I/O & Peripheral Pin PE4 (SPI) |
| 4 | PE5 | I/O | Multiplexed I/O & Peripheral Pin PE5 (SPI) |
| 5 | PE6 | I/O | Multiplexed I/O & Peripheral Pin PE6 (PWM) |
| 6 | VBAT | Power | Power Supply Input (VBAT — 3.3V VDD (Max 4.0V)) |
| 7 | PC13 | I/O | Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK) |
| 8 | PC14 - OSC32 IN(PC14)_ | I/O | Multiplexed I/O & Peripheral Pin PC14 - OSC32 IN(PC14)_ (RTC/CLK) |
| 9 | IO4 | I/O | GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3 |
| 10 | PF0 | I/O | Multiplexed I/O & Peripheral Pin PF0 (I2C) |
| 11 | PF1 | I/O | Multiplexed I/O & Peripheral Pin PF1 (I2C) |
| 12 | PF2 | I/O | Multiplexed I/O & Peripheral Pin PF2 (I2C) |
| 13 | PF3 | I/O | Multiplexed I/O & Peripheral Pin PF3 (ADC) |
| 14 | PF4 | I/O | Multiplexed I/O & Peripheral Pin PF4 (ADC) |
| 15 | PF5 | I/O | Multiplexed I/O & Peripheral Pin PF5 (ADC) |
| 16 | VSS | GND | Ground Reference Pin (VSS) |
| 17 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 18 | PF6 | I/O | Multiplexed I/O & Peripheral Pin PF6 (ADC) |
| 19 | PF7 | I/O | Multiplexed I/O & Peripheral Pin PF7 (ADC) |
| 20 | PF8 | I/O | Multiplexed I/O & Peripheral Pin PF8 (UART, SPI, ADC) |
| 21 | PF9 | I/O | Multiplexed I/O & Peripheral Pin PF9 (UART, SPI, ADC) |
| 22 | PF10 | I/O | Multiplexed I/O & Peripheral Pin PF10 (ADC) |
| 23 | PH0OSC IN -_ | I/O | Multiplexed I/O & Peripheral Pin PH0OSC IN -_ (RTC/CLK) |
| 24 | PH1OSC OUT -_ | I/O | Multiplexed I/O & Peripheral Pin PH1OSC OUT -_ (RTC/CLK) |
| 25 | NRST | I | System Enable & Hardware Reset (NRST) |
| 26 | PC0 | I/O | Multiplexed I/O & Peripheral Pin PC0 (ADC) |
| 27 | PC1 | I/O | Multiplexed I/O & Peripheral Pin PC1 (SPI, I2C, ADC, RTC/CLK) |
| 28 | PC2 | I/O | Multiplexed I/O & Peripheral Pin PC2 (SPI, ADC) |
| 29 | PC3 | I/O | Multiplexed I/O & Peripheral Pin PC3 (SPI, ADC) |
| 30 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 31 | VSSA | GND | Ground Reference Pin (VSSA) |
| 32 | VREF+ | Analog | Multiplexed I/O & Peripheral Pin VREF+ (General) |
| 33 | VDDA | Power | Power Supply Input (VDDA — 3.3V VDD (Max 4.0V)) |
| 34 | PA0WKUP - | I/O | Multiplexed I/O & Peripheral Pin PA0WKUP - (UART, ADC, PWM) |
| 35 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM) |
| 36 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (SPI, ADC, PWM) |
| 37 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (ADC, PWM) |
| 38 | VSS | GND | Ground Reference Pin (VSS) |
| 39 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 40 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC) |
| 41 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC) |
| 42 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (ADC) |
| 43 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM) |
| 44 | PC4 | I/O | Multiplexed I/O & Peripheral Pin PC4 (ADC) |
| 45 | PC5 | I/O | Multiplexed I/O & Peripheral Pin PC5 (ADC) |
| 46 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (ADC, PWM) |
| 47 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (ADC, PWM) |
| 48 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (SPI, I2C) |
| 49 | PF11 | I/O | Multiplexed I/O & Peripheral Pin PF11 (SPI) |
| 50 | PF12 | I/O | Multiplexed I/O & Peripheral Pin PF12 (General) |
| 51 | VSS | GND | Ground Reference Pin (VSS) |
| 52 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 53 | PF13 | I/O | Multiplexed I/O & Peripheral Pin PF13 (General) |
| 54 | PF14 | I/O | Multiplexed I/O & Peripheral Pin PF14 (General) |
| 55 | PF15 | I/O | Multiplexed I/O & Peripheral Pin PF15 (General) |
| 56 | PG0 | I/O | Multiplexed I/O & Peripheral Pin PG0 (General) |
| 57 | PG1 | I/O | Multiplexed I/O & Peripheral Pin PG1 (General) |
| 58 | PE7 | I/O | Multiplexed I/O & Peripheral Pin PE7 (General) |
| 59 | PE8 | I/O | Multiplexed I/O & Peripheral Pin PE8 (PWM) |
| 60 | PE9 | I/O | Multiplexed I/O & Peripheral Pin PE9 (PWM) |
| 61 | VSS | GND | Ground Reference Pin (VSS) |
| 62 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 63 | PE10 | I/O | Multiplexed I/O & Peripheral Pin PE10 (PWM) |
| 64 | PE11 | I/O | Multiplexed I/O & Peripheral Pin PE11 (PWM) |
| 65 | PE12 | I/O | Multiplexed I/O & Peripheral Pin PE12 (SPI, PWM) |
| 66 | PE13 | I/O | Multiplexed I/O & Peripheral Pin PE13 (PWM) |
| 67 | PE14 | I/O | Multiplexed I/O & Peripheral Pin PE14 (PWM) |
| 68 | PE15 | I/O | Multiplexed I/O & Peripheral Pin PE15 (General) |
| 69 | PB10 | I/O | Multiplexed I/O & Peripheral Pin PB10 (UART, SPI, PWM) |
| 70 | PB11 | I/O | Multiplexed I/O & Peripheral Pin PB11 (UART, PWM) |
| 71 | VCAP_1 | I/O | Multiplexed I/O & Peripheral Pin VCAP_1 (General) |
| 72 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 73 | PB12 | I/O | Multiplexed I/O & Peripheral Pin PB12 (UART, SPI) |
| 74 | PB13 | I/O | Multiplexed I/O & Peripheral Pin PB13 (UART, SPI) |
| 75 | OTG_HSREXT_ | I/O | Multiplexed I/O & Peripheral Pin OTG_HSREXT_ (USB) |
| 76 | VDD12OTGHS | Power | Power Supply Input (VDD12OTGHS — 3.3V VDD (Max 4.0V)) |
| 77 | PB14 | I/O | Multiplexed I/O & Peripheral Pin PB14 (General) |
| 78 | PB15 | I/O | Multiplexed I/O & Peripheral Pin PB15 (General) |
| 79 | PD8 | I/O | Multiplexed I/O & Peripheral Pin PD8 (UART) |
| 80 | PD9 | I/O | Multiplexed I/O & Peripheral Pin PD9 (UART) |
| 81 | PD10 | I/O | Multiplexed I/O & Peripheral Pin PD10 (UART) |
| 82 | PD11 | I/O | Multiplexed I/O & Peripheral Pin PD11 (UART) |
| 83 | PD12 | I/O | Multiplexed I/O & Peripheral Pin PD12 (UART, PWM) |
| 84 | PD13 | I/O | Multiplexed I/O & Peripheral Pin PD13 (SPI, PWM) |
| 85 | VSS | GND | Ground Reference Pin (VSS) |
| 86 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 87 | PD14 | I/O | Multiplexed I/O & Peripheral Pin PD14 (PWM) |
| 88 | PD15 | I/O | Multiplexed I/O & Peripheral Pin PD15 (PWM) |
| 89 | PG2 | I/O | Multiplexed I/O & Peripheral Pin PG2 (General) |
| 90 | PG3 | I/O | Multiplexed I/O & Peripheral Pin PG3 (General) |
| 91 | PG4 | I/O | Multiplexed I/O & Peripheral Pin PG4 (General) |
| 92 | PG5 | I/O | Multiplexed I/O & Peripheral Pin PG5 (General) |
| 93 | PG8 | I/O | Multiplexed I/O & Peripheral Pin PG8 (UART) |
| 94 | VSS | GND | Ground Reference Pin (VSS) |
| 95 | VDDUSB | Power | Power Supply Input (VDDUSB — 3.3V VDD (Max 4.0V)) |
| 96 | PC6 | I/O | Multiplexed I/O & Peripheral Pin PC6 (PWM) |
| 97 | PC7 | I/O | Multiplexed I/O & Peripheral Pin PC7 (PWM) |
| 98 | PC8 | I/O | Multiplexed I/O & Peripheral Pin PC8 (UART, PWM) |
| 99 | PC9 | I/O | Multiplexed I/O & Peripheral Pin PC9 (UART, I2C, RTC/CLK) |
| 100 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (I2C, RTC/CLK) |
| 101 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (UART, SPI, PWM) |
| 102 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (PWM) |
| 103 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (PWM, CAN) |
| 104 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (General) |
| 105 | PA13(JTMSSWDIO) - | I/O | Multiplexed I/O & Peripheral Pin PA13(JTMSSWDIO) - (SWD/JTAG) |
| 106 | VCAP_2 | I/O | Multiplexed I/O & Peripheral Pin VCAP_2 (General) |
| 107 | VSS | GND | Ground Reference Pin (VSS) |
| 108 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 109 | PA14(JTCK - SWCLK) | I/O | Multiplexed I/O & Peripheral Pin PA14(JTCK - SWCLK) (SWD/JTAG) |
| 110 | PA15(JTDI) | I/O | Multiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG) |
| 111 | PC10 | I/O | Multiplexed I/O & Peripheral Pin PC10 (UART, SPI) |
| 112 | PC11 | I/O | Multiplexed I/O & Peripheral Pin PC11 (UART, SPI) |
| 113 | PC12 | I/O | Multiplexed I/O & Peripheral Pin PC12 (UART, SPI) |
| 114 | PD0 | I/O | Multiplexed I/O & Peripheral Pin PD0 (CAN) |
| 115 | PD1 | I/O | Multiplexed I/O & Peripheral Pin PD1 (CAN) |
| 116 | PD2 | I/O | Multiplexed I/O & Peripheral Pin PD2 (UART) |
| 117 | PD3 | I/O | Multiplexed I/O & Peripheral Pin PD3 (UART, SPI) |
| 118 | PD4 | I/O | Multiplexed I/O & Peripheral Pin PD4 (UART) |
| 119 | PD5 | I/O | Multiplexed I/O & Peripheral Pin PD5 (UART) |
| 120 | VSS | GND | Ground Reference Pin (VSS) |
| 121 | VDDSDMMC | Power | Power Supply Input (VDDSDMMC — 3.3V VDD (Max 4.0V)) |
| 122 | PD6 | I/O | Multiplexed I/O & Peripheral Pin PD6 (SPI) |
| 123 | PD7 | I/O | Multiplexed I/O & Peripheral Pin PD7 (UART) |
| 124 | PG9 | I/O | Multiplexed I/O & Peripheral Pin PG9 (UART) |
| 125 | PG10 | I/O | Multiplexed I/O & Peripheral Pin PG10 (General) |
| 126 | PG11 | I/O | Multiplexed I/O & Peripheral Pin PG11 (General) |
| 127 | PG12 | I/O | Multiplexed I/O & Peripheral Pin PG12 (General) |
| 128 | PG13 | I/O | Multiplexed I/O & Peripheral Pin PG13 (UART) |
| 129 | PG14 | I/O | Multiplexed I/O & Peripheral Pin PG14 (UART) |
| 130 | VSS | GND | Ground Reference Pin (VSS) |
| 131 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 132 | PG15 | I/O | Multiplexed I/O & Peripheral Pin PG15 (UART) |
| 133 | PB3(JTDO/TRACES WO) | I/O | Multiplexed I/O & Peripheral Pin PB3(JTDO/TRACES WO) (SPI, SWD/JTAG) |
| 134 | PB4(NJTRST) | I/O | Multiplexed I/O & Peripheral Pin PB4(NJTRST) (SPI, SWD/JTAG) |
| 135 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (SPI, PWM) |
| 136 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (UART, PWM) |
| 137 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (UART, PWM) |
| 138 | BOOT | I/O | Multiplexed I/O & Peripheral Pin BOOT (General) |
| 139 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (I2C, PWM) |
| 140 | PB9 | I/O | Multiplexed I/O & Peripheral Pin PB9 (SPI, I2C, PWM, CAN) |
| 141 | PE0 | I/O | Multiplexed I/O & Peripheral Pin PE0 (UART) |
| 142 | PE1 | I/O | Multiplexed I/O & Peripheral Pin PE1 (General) |
| 143 | PDR_ON | I/O | Multiplexed I/O & Peripheral Pin PDR_ON (General) |
| 144 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
PIN 1 PE2
I/OMultiplexed I/O & Peripheral Pin PE2 (SPI)
Design note: Alt: TRACECLK SPI4 SCK ,_ , SAI1_MCLKA_ , QUADSPI BK1_IO2FMCA23_ ,_ , EVENTOUT
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 20 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (144 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-144(20x20) · 20.00×20.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (144 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (20 figures · Page 1/2)
Showing 1–12 of 20 uncropped original figures for STM32F730
P52 · p52_fig01EXACT PACKAGE
P191 · p191_fig01EXACT PACKAGE
P192 · p192_fig01EXACT PACKAGE
P1 · p01_fig01881×596px
P86 · p86_fig011546×1696px
P87 · p87_fig011875×2491px
P117 · p117_fig011546×487px
P142 · p142_fig011546×1229px
P142 · p142_fig021546×604px
P186 · p186_fig01All Packages in PDF
P50 · p50_fig01EXACT PACKAGE
P185 · p185_fig01EXACT PACKAGE
Page 1 / 2 (20 extracted figures)
Technical Specifications & Part Details (STM32F730Z8T6)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32F730Z8T6 (LQFP-144(20x20)) is a 144-pin embedded microcontroller unit (mcu) featuring a 20.00 × 20.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.7 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, CAN, DAC, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.7 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
216 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
110 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
20.00 × 20.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-144(20x20))
Pin Count & Lead PitchN / e
144 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, CAN, DAC, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol144 auto-grouped pins
IPC-7351B Land Pattern144 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32F730 (5)
LQFP-100(14x14) · 100P
LQFP-144(20x20) · 144P
QFP-144(20x20) · 144P
UFBGA-201 · 201P
Mechanical Dimensions & Land Pattern (LQFP-144(20x20))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
20.00 × 20.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.35 × 1.35 mm
Pins / Total PadsTopology
144P / 144Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-144(20x20) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32F730Z8T6 (LQFP-144(20x20))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32F730Z8T6 (LQFP-144(20x20))?
Manufactured by ST, the STM32F730Z8T6 is housed in a LQFP-144(20x20) package with 144 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (SPI)), 2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), 3 (PE4: Multiplexed I/O & Peripheral Pin PE4 (SPI)), 4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (SPI)), 5 (PE6: Multiplexed I/O & Peripheral Pin PE6 (PWM)), 6 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))).
What are the IPC-7351B PCB Footprint dimensions for STM32F730Z8T6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F730Z8T6 (LQFP-144(20x20)) has a nominal body envelope of 20.00 × 20.00 mm, pitch e = 0.50 mm, and 144 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F730Z8T6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F730Z8T6 (ST, LQFP-144(20x20)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (144 pins) & STM32F730 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PE2 | Digital_IO | Signal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_SCK. Supported peripheral buses: SPI. |
| 2 | PE3 | Digital_IO | Signal terminal PE3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General. |
| 3 | PE4 | Digital_IO | Signal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSS. Supported peripheral buses: SPI. |
| 4 | PE5 | Digital_IO | Signal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MISO_SAI1SCKA. Supported peripheral buses: SPI. |
| 5 | PE6 | Digital_IO | Signal terminal PE6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: PWM. |
| 6 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 7 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| 8 | PC14 - OSC32 IN(PC14)_ | Digital_IO | Signal terminal PC14 - OSC32 IN(PC14)_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32 IN(PC14)_. Supported peripheral buses: RTC/CLK. |
| 9 | IO4 | Digital_IO | GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3 |
| 10 | PF0 | Digital_IO | Signal terminal PF0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF0. Supported peripheral buses: I2C. |
| 11 | PF1 | Digital_IO | Signal terminal PF1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: I2C. |
| 12 | PF2 | Digital_IO | Signal terminal PF2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: I2C. |
| 13 | PF3 | Digital_IO | Signal terminal PF3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: ADC. |
| 14 | PF4 | Digital_IO | Signal terminal PF4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: ADC. |
| 15 | PF5 | Digital_IO | Signal terminal PF5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: ADC. |
| 16 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 17 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 18 | PF6 | Digital_IO | Signal terminal PF6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF6. Supported peripheral buses: ADC. |
| 19 | PF7 | Digital_IO | Signal terminal PF7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF7. Supported peripheral buses: ADC. |
| 20 | PF8 | Digital_IO | Signal terminal PF8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI5_MISO_SAI1SCKB. Supported peripheral buses: UART, SPI, ADC. |
| 21 | PF9 | Digital_IO | Signal terminal PF9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI5_MOSI_SAI1FSB. Supported peripheral buses: UART, SPI, ADC. |
| 22 | PF10 | Digital_IO | Signal terminal PF10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF10. Supported peripheral buses: ADC. |
| 23 | PH0OSC IN -_ | Digital_IO | Signal terminal PH0OSC IN -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0OSC IN -_. Supported peripheral buses: RTC/CLK. |
| 24 | PH1OSC OUT -_ | Digital_IO | Signal terminal PH1OSC OUT -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1OSC OUT -_. Supported peripheral buses: RTC/CLK. |
| 25 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 26 | PC0 | Digital_IO | Signal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC. |
| 27 | PC1 | Digital_IO | Signal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, I2C, ADC, RTC/CLK. |
| 28 | PC2 | Digital_IO | Signal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, ADC. |
| 29 | PC3 | Digital_IO | Signal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC. |
| 30 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 31 | VSSA | GND | 0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| 32 | VREF+ | Analog | Signal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General. |
| 33 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 34 | PA0WKUP - | Digital_IO | Signal terminal PA0WKUP - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0WKUP -. Supported peripheral buses: UART, ADC, PWM. |
| 35 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM. |
| 36 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: SPI, ADC, PWM. |
| 37 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: ADC, PWM. |
| 38 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 39 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 40 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, ADC, DAC. |
| 41 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC. |
| 42 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: ADC. |
| 43 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM. |
| 44 | PC4 | Digital_IO | Signal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC. |
| 45 | PC5 | Digital_IO | Signal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC. |
| 46 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM. |
| 47 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM. |
| 48 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: SPI, I2C. |
| 49 | PF11 | Digital_IO | Signal terminal PF11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI5_MOSI_SAI2SDB. Supported peripheral buses: SPI. |
| 50 | PF12 | Digital_IO | Signal terminal PF12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF12. Supported peripheral buses: General. |
| 51 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 52 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 53 | PF13 | Digital_IO | Signal terminal PF13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF13. Supported peripheral buses: General. |
| 54 | PF14 | Digital_IO | Signal terminal PF14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF14. Supported peripheral buses: General. |
| 55 | PF15 | Digital_IO | Signal terminal PF15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF15. Supported peripheral buses: General. |
| 56 | PG0 | Digital_IO | Signal terminal PG0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG0. Supported peripheral buses: General. |
| 57 | PG1 | Digital_IO | Signal terminal PG1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG1. Supported peripheral buses: General. |
| 58 | PE7 | Digital_IO | Signal terminal PE7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General. |
| 59 | PE8 | Digital_IO | Signal terminal PE8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: PWM. |
| 60 | PE9 | Digital_IO | Signal terminal PE9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE9. Supported peripheral buses: PWM. |
| 61 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 62 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 63 | PE10 | Digital_IO | Signal terminal PE10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE10. Supported peripheral buses: PWM. |
| 64 | PE11 | Digital_IO | Signal terminal PE11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE11. Supported peripheral buses: PWM. |