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STM32F469VGT6 (LQFP-100(14x14)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F469VGT6

STID: C503095LQFP-100(14x14) · 100 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F469VGT6 (LQFP-100(14x14))1PE22VSS3VBAT4PC135PC14OSC32 IN6IO37VSS8VDD9PH0OSC IN -_10PH1OSC OUT -11NRST12PC013PC114PC215PC316VSSA17VREF+18VDDA19PA0WKUP(PA0)20PA121PA222PA323VSS24VDD25PA426PA527PA628PA729PB030PB131PB2 - BOOT1(32PE733PE834PE935PE1036PE1137PE1238PE1339PE1440PE1541PB1042PB1143VCAP144VSS45VDD46PB1247PB1348PB1449PB1550PD8100VDD99PB998PB897BOOT096PB795PB694PB593PB4(NJTRST)92PB3(JTDO/TRA91PD790PD689PD588PD487PD386PD285PD184PD083PC1282PC1181PC1080PA15(JTDI)79PA14(JTCK - 78VSS77VDD76VCAP275PA13(JTMS - 74PA1273PA1172PA1071PA970PA869PC968PC867PC766PC665VDDUSB64DSIHOST_D1N63DSIHOST_D1P62VDD12DSI61DSIHOST_CKN60DSIHOST_CKP59VSSDSI58DSIHOST_D0N57DSIHOST_D0P56VCAPDSI55VDDDSI54PD1553PD1452PD1051PD9Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100E=14.00mm · Pitch e=0.50mmD=14.00mm-12-10-8-6-4-2024681012121086420-2-4-6-8-10-12mm
3. 3D CAD MODEL
Package Body: 14.00mm × 14.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PE2I/OMultiplexed I/O & Peripheral Pin PE2 (UART, SPI)
2VSSGNDGround Reference Pin (VSS)
3VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
4PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
5PC14OSC32 IN -_ (PC14)I/OMultiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (PC14) (RTC/CLK)
6IO3I/OGPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)
7VSSGNDGround Reference Pin (VSS)
8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
9PH0OSC IN -_ (PH0)I/OMultiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (RTC/CLK)
10PH1OSC OUT -_ (PH1)I/OMultiplexed I/O & Peripheral Pin PH1OSC OUT -_ (PH1) (RTC/CLK)
11NRSTISystem Enable & Hardware Reset (NRST)
12PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
13PC1I/OMultiplexed I/O & Peripheral Pin PC1 (SPI, ADC)
14PC2I/OMultiplexed I/O & Peripheral Pin PC2 (SPI, ADC)
15PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI, ADC)
16VSSAGNDGround Reference Pin (VSSA)
17VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
18VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
19PA0WKUP(PA0) -I/OMultiplexed I/O & Peripheral Pin PA0WKUP(PA0) - (UART, ADC, PWM)
20PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
21PA2I/OMultiplexed I/O & Peripheral Pin PA2 (ADC, PWM)
22PA3I/OMultiplexed I/O & Peripheral Pin PA3 (ADC, PWM)
23VSSGNDGround Reference Pin (VSS)
24VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
25PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
26PA5I/OMultiplexed I/O & Peripheral Pin PA5 (ADC, DAC, PWM)
27PA6I/OMultiplexed I/O & Peripheral Pin PA6 (ADC)
28PA7I/OMultiplexed I/O & Peripheral Pin PA7 (ADC, PWM)
29PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, ADC, PWM)
30PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
31PB2 - BOOT1(PB2)I/OMultiplexed I/O & Peripheral Pin PB2 - BOOT1(PB2) (General)
32PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
33PE8I/OMultiplexed I/O & Peripheral Pin PE8 (PWM)
34PE9I/OMultiplexed I/O & Peripheral Pin PE9 (PWM)
35PE10I/OMultiplexed I/O & Peripheral Pin PE10 (PWM)
36PE11I/OMultiplexed I/O & Peripheral Pin PE11 (PWM)
37PE12I/OMultiplexed I/O & Peripheral Pin PE12 (PWM)
38PE13I/OMultiplexed I/O & Peripheral Pin PE13 (PWM)
39PE14I/OMultiplexed I/O & Peripheral Pin PE14 (PWM)
40PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
41PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, SPI, PWM)
42PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, PWM)
43VCAP1I/OMultiplexed I/O & Peripheral Pin VCAP1 (General)
44VSSGNDGround Reference Pin (VSS)
45VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
46PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI)
47PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
48PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
49PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM, RTC/CLK)
50PD8I/OMultiplexed I/O & Peripheral Pin PD8 (UART)
51PD9I/OMultiplexed I/O & Peripheral Pin PD9 (UART)
52PD10I/OMultiplexed I/O & Peripheral Pin PD10 (UART)
53PD14I/OMultiplexed I/O & Peripheral Pin PD14 (PWM)
54PD15I/OMultiplexed I/O & Peripheral Pin PD15 (PWM)
55VDDDSIPowerPower Supply Input (VDDDSI — 3.3V VDD (Max 4.0V))
56VCAPDSII/OMultiplexed I/O & Peripheral Pin VCAPDSI (General)
57DSIHOST_D0PI/OMultiplexed I/O & Peripheral Pin DSIHOST_D0P (General)
58DSIHOST_D0NI/OMultiplexed I/O & Peripheral Pin DSIHOST_D0N (General)
59VSSDSIGNDGround Reference Pin (VSSDSI)
60DSIHOST_CKPI/OMultiplexed I/O & Peripheral Pin DSIHOST_CKP (General)
61DSIHOST_CKNI/OMultiplexed I/O & Peripheral Pin DSIHOST_CKN (General)
62VDD12DSIPowerPower Supply Input (VDD12DSI — 3.3V VDD (Max 4.0V))
63DSIHOST_D1PI/OMultiplexed I/O & Peripheral Pin DSIHOST_D1P (General)
64DSIHOST_D1NI/OMultiplexed I/O & Peripheral Pin DSIHOST_D1N (General)
65VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
66PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
67PC7I/OMultiplexed I/O & Peripheral Pin PC7 (PWM)
68PC8I/OMultiplexed I/O & Peripheral Pin PC8 (PWM)
69PC9I/OMultiplexed I/O & Peripheral Pin PC9 (PWM, RTC/CLK)
70PA8I/OMultiplexed I/O & Peripheral Pin PA8 (I2C, RTC/CLK)
71PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, SPI, PWM)
72PA10I/OMultiplexed I/O & Peripheral Pin PA10 (PWM)
73PA11I/OMultiplexed I/O & Peripheral Pin PA11 (PWM, CAN)
74PA12I/OMultiplexed I/O & Peripheral Pin PA12 (CAN)
75PA13(JTMS - SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13(JTMS - SWDIO) (SWD/JTAG)
76VCAP2I/OMultiplexed I/O & Peripheral Pin VCAP2 (General)
77VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
78VSSGNDGround Reference Pin (VSS)
79PA14(JTCK - SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14(JTCK - SWCLK) (SWD/JTAG)
80PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (SPI, SWD/JTAG)
81PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
82PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART)
83PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI)
84PD0I/OMultiplexed I/O & Peripheral Pin PD0 (CAN)
85PD1I/OMultiplexed I/O & Peripheral Pin PD1 (CAN)
86PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
87PD3I/OMultiplexed I/O & Peripheral Pin PD3 (UART, SPI)
88PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART)
89PD5I/OMultiplexed I/O & Peripheral Pin PD5 (UART)
90PD6I/OMultiplexed I/O & Peripheral Pin PD6 (SPI)
91PD7I/OMultiplexed I/O & Peripheral Pin PD7 (UART)
92PB3(JTDO/TRA CESWO)I/OMultiplexed I/O & Peripheral Pin PB3(JTDO/TRA CESWO) (SPI, PWM, SWD/JTAG)
93PB4(NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4(NJTRST) (SPI, SWD/JTAG)
94PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, PWM, CAN)
95PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, PWM)
96PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, PWM)
97BOOT0IInput-Only Pin BOOT0 (General)
98PB8I/OMultiplexed I/O & Peripheral Pin PB8 (UART, I2C, PWM)
99PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI, I2C, PWM, CAN)
100VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
PIN 1 PE2
I/O
Multiplexed I/O & Peripheral Pin PE2 (UART, SPI)
Design note: Alt: TRACECLK SPI4 SCK ,_ , SAI1_MCLKA_ , QUADSPI_BK1IO2_ , ETH MII_TXD3FMCA23_ ,_ , EVENTOUT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 17 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F469VGT6 (ST · LQFP-100(14x14))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F469VGT6 (LQFP-100(14x14)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F469VGT6 (LQFP-100(14x14)) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F469VGT6 (LQFP-100(14x14)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F469VGT6 (LQFP-100(14x14)) - 4. Package Dimensions (D×E×A)
LQFP-100(14x14) · 14.00×14.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F469VGT6 (LQFP-100(14x14)) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F469VGT6 (LQFP-100(14x14)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (17 figures · Page 1/2)
Showing 1–12 of 17 uncropped original figures for STM32F469
P48 · p48_fig01EXACT PACKAGE
STM32F469VGT6 (LQFP-100(14x14)) — Figure 13. STM32F46x LQFP100 pinout %227 
Figure 13. STM32F46x LQFP100 pinout %227 
P192 · p192_fig01EXACT PACKAGE
STM32F469VGT6 (LQFP-100(14x14)) — Figure 80. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline
Figure 80. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline
P194 · p194_fig01EXACT PACKAGE
STM32F469VGT6 (LQFP-100(14x14)) — Figure 81. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
Figure 81. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
P194 · p194_fig02EXACT PACKAGE
STM32F469VGT6 (LQFP-100(14x14)) — Figure 82. LQFP100 marking example (package top view)
Figure 82. LQFP100 marking example (package top view)
P1 · p01_fig02883×395px
STM32F469VGT6 (LQFP-100(14x14)) — May 2018 DS11189 Rev 5 1/219
May 2018 DS11189 Rev 5 1/219
P48 · p48_fig01P48
STM32F469VGT6 (LQFP-100(14x14)) — Datasheet Page 48 (p48_fig01)
Datasheet Page 48 (p48_fig01)
P54 · p54_fig011751×1626px
STM32F469VGT6 (LQFP-100(14x14)) — Figure 19. STM32F46x LQFP208 pinout
Figure 19. STM32F46x LQFP208 pinout
P90 · p90_fig011546×1725px
STM32F469VGT6 (LQFP-100(14x14)) — Figure 24. Power supply scheme
Figure 24. Power supply scheme
P90 · p90_fig01P90
STM32F469VGT6 (LQFP-100(14x14)) — Datasheet Page 90 (p90_fig01)
Datasheet Page 90 (p90_fig01)
P117 · p117_fig011546×497px
STM32F469VGT6 (LQFP-100(14x14)) — Figure 31. Typical application with an 8 MHz crystal
Figure 31. Typical application with an 8 MHz crystal
P118 · p118_fig011546×517px
STM32F469VGT6 (LQFP-100(14x14)) — Figure 32. Typical application with a 32.768 kHz crystal
Figure 32. Typical application with a 32.768 kHz crystal
P160 · p160_fig011546×1229px
STM32F469VGT6 (LQFP-100(14x14)) — Figure 54. ADC accuracy characteristics
Figure 54. ADC accuracy characteristics
Page 1 / 2 (17 extracted figures)

Technical Specifications & Part Details (STM32F469VGT6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F469VGT6 (LQFP-100(14x14)) is a 100-pin embedded microcontroller unit (mcu) featuring a 14.00 × 14.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.7 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, CAN, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.7 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
180 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
69 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
14.00 × 14.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-100(14x14))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, CAN, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2 - BOOT1(PB2), BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-100(14x14))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-100(14x14)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F469VGT6 (LQFP-100(14x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F469VGT6 (LQFP-100(14x14))?

Manufactured by ST, the STM32F469VGT6 is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (UART, SPI)), 2 (VSS: Ground Reference Pin (VSS)), 3 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 4 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 5 (PC14OSC32 IN -_ (PC14): Multiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (PC14) (RTC/CLK)), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).

What are the IPC-7351B PCB Footprint dimensions for STM32F469VGT6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F469VGT6 (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F469VGT6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F469VGT6 (ST, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32F469 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_SCK. Supported peripheral buses: UART, SPI.
2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
3VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
4PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
5PC14OSC32 IN -_ (PC14)Digital_IOSignal terminal PC14OSC32 IN -_ (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14OSC32 IN -_ (PC14). Supported peripheral buses: RTC/CLK.
6IO3Digital_IOGPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)
7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
8VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
9PH0OSC IN -_ (PH0)Digital_IOSignal terminal PH0OSC IN -_ (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0OSC IN -_ (PH0). Supported peripheral buses: RTC/CLK.
10PH1OSC OUT -_ (PH1)Digital_IOSignal terminal PH1OSC OUT -_ (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1OSC OUT -_ (PH1). Supported peripheral buses: RTC/CLK.
11NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
12PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
13PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC.
14PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOI2S2EXTSD. Supported peripheral buses: SPI, ADC.
15PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC.
16VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
17VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
18VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
19PA0WKUP(PA0) -Digital_IOSignal terminal PA0WKUP(PA0) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0WKUP(PA0) -. Supported peripheral buses: UART, ADC, PWM.
20PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
21PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: ADC, PWM.
22PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: ADC, PWM.
23VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
24VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
25PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
26PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: ADC, DAC, PWM.
27PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: ADC.
28PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: ADC, PWM.
29PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: UART, ADC, PWM.
30PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM.
31PB2 - BOOT1(PB2)Digital_IOSignal terminal PB2 - BOOT1(PB2) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2 - BOOT1(PB2). Supported peripheral buses: General.
32PE7Digital_IOSignal terminal PE7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
33PE8Digital_IOSignal terminal PE8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: PWM.
34PE9Digital_IOSignal terminal PE9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE9. Supported peripheral buses: PWM.
35PE10Digital_IOSignal terminal PE10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE10. Supported peripheral buses: PWM.
36PE11Digital_IOSignal terminal PE11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE11. Supported peripheral buses: PWM.
37PE12Digital_IOSignal terminal PE12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE12. Supported peripheral buses: PWM.
38PE13Digital_IOSignal terminal PE13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE13. Supported peripheral buses: PWM.
39PE14Digital_IOSignal terminal PE14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE14. Supported peripheral buses: PWM.
40PE15Digital_IOSignal terminal PE15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE15. Supported peripheral buses: General.
41PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
42PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: UART, PWM.
43VCAP1Digital_IOSignal terminal VCAP1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP1. Supported peripheral buses: General.
44VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
45VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
46PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI.
47PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
48PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOI2S2EXTSD. Supported peripheral buses: UART, SPI, PWM.
49PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, PWM, RTC/CLK.
50PD8Digital_IOSignal terminal PD8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD8. Supported peripheral buses: UART.
51PD9Digital_IOSignal terminal PD9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD9. Supported peripheral buses: UART.
52PD10Digital_IOSignal terminal PD10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: UART.
53PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: PWM.
54PD15Digital_IOSignal terminal PD15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: PWM.
55VDDDSIPower_InPrimary positive power supply input (VDDDSI) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
56VCAPDSIDigital_IOSignal terminal VCAPDSI (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAPDSI. Supported peripheral buses: General.
57DSIHOST_D0PDigital_IOSignal terminal DSIHOST_D0P (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DSIHOST_D0P. Supported peripheral buses: General.
58DSIHOST_D0NDigital_IOSignal terminal DSIHOST_D0N (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DSIHOST_D0N. Supported peripheral buses: General.
59VSSDSIGND0V electrical ground return terminal (VSSDSI) for internal core logic, I/O drivers, and analog sub-blocks.
60DSIHOST_CKPDigital_IOSignal terminal DSIHOST_CKP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DSIHOST_CKP. Supported peripheral buses: General.
61DSIHOST_CKNDigital_IOSignal terminal DSIHOST_CKN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DSIHOST_CKN. Supported peripheral buses: General.
62VDD12DSIPower_InPrimary positive power supply input (VDD12DSI) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
63DSIHOST_D1PDigital_IOSignal terminal DSIHOST_D1P (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DSIHOST_D1P. Supported peripheral buses: General.
64DSIHOST_D1NDigital_IOSignal terminal DSIHOST_D1N (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DSIHOST_D1N. Supported peripheral buses: General.
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