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STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32U375RGY6QTR

STID: C45338538WLCSP-68(3.1x3.2) · 68 Pins · Pitch 0.35mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32U375RGY6QTR (WLCSP-68(3.1x3.2))A1VDDA3PA15(JTDI)A5PB5A7PB9A9VDDB2VDDUSBB4PB3(JTDO/ TRB6PB8B8VDDC1PA12C3PA14(JTCK/ SC5PH3BOOT0 - (C7VSSC9PB9D2VSSD4PB4(NJTRST)D6VBATD8IOD8E1PA11E3PA13(JTMS/ SE5PB7E7IOE7E9PC14-OSC32_IF2PA10F4PB6F6PC13F8PH0OSC IN (-G1PB15G3PA9G5PA1G7PH1 - OSC OUG9PH0-OSC_INH2PA8H4PA2R9VDDR7PA7R5PB2R3VDDSMPSR1VDDP8VSSP6PA4P4VLXSMPSP2VDD11N9VDDAN7VDDN5PB2N3VDDSMPSN1VDDM8PA3M6PA6M4VLXSMPSM2VDD11L9PC3L7VSSL5PB1L3VSSSMPSL1VSSK8VDDAK6PA4K4PB0K2PB13J9NRSTJ7VSSAJ5PA5J3PA7J1PB14H8NRST(NRST)H6PA0Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.848.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3mm
2. 2D FOOTPRINT
A1C1E1G1J1L1N1R1B2D2F2H2K2M2P2A3C3E3G3J3L3N3R3B4D4F4H4K4M4P4A5C5E5G5J5L5N5R5B6D6F6H6K6M6P6A7C7E7G7J7L7N7R7B8D8F8H8K8M8P8A9C9E9G9J9L9N9R9E=3.20mm · Pitch e=0.35mmD=3.10mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 3.20mm × 3.10mm · Pitch: 0.35mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (68/68)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
A3PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG)
A5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C)
A7PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI)
A9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
B2VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
B4PB3(JTDO/ TRACESWO)I/OMultiplexed I/O & Peripheral Pin PB3(JTDO/ TRACESWO) (SPI, I2C, SWD/JTAG)
B6PB8I/OMultiplexed I/O & Peripheral Pin PB8 (SPI, I2C)
B8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
C1PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, SPI)
C3PA14(JTCK/ SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14(JTCK/ SWCLK) (I2C, SWD/JTAG)
C5PH3BOOT0 - (PH3)I/OMultiplexed I/O & Peripheral Pin PH3BOOT0 - (PH3) (I2C)
C7VSSGNDGround Reference Pin (VSS)
C9PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
D2VSSGNDGround Reference Pin (VSS)
D4PB4(NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4(NJTRST) (UART, SPI, I2C, SWD/JTAG)
D6VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
D8IOD8I/OGeneral Purpose Digital I/O Pin IOD8
E1PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, SPI)
E3PA13(JTMS/ SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13(JTMS/ SWDIO) (USB, SWD/JTAG)
E5PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
E7IOE7I/OGeneral Purpose Digital I/O Pin IOE7
E9PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
F2PA10I/OMultiplexed I/O & Peripheral Pin PA10 (RTC/CLK)
F4PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C, PWM)
F6PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
F8PH0OSC IN (- PH0)_I/OMultiplexed I/O & Peripheral Pin PH0OSC IN (- PH0)_ (RTC/CLK)
G1PB15I/OMultiplexed I/O & Peripheral Pin PB15 (PWM, RTC/CLK)
G3PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, SPI, RTC/CLK)
G5PA1I/OMultiplexed I/O & Peripheral Pin PA1 (SPI, I2C)
G7PH1 - OSC OUT (PH_1)I/OMultiplexed I/O & Peripheral Pin PH1 - OSC OUT (PH_1) (RTC/CLK)
G9PH0-OSC_INI/OMultiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK)
H2PA8I/OMultiplexed I/O & Peripheral Pin PA8 (SPI, RTC/CLK)
H4PA2I/OMultiplexed I/O & Peripheral Pin PA2 (SPI)
H6PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, SPI)
H8NRST(NRST)I/OMultiplexed I/O & Peripheral Pin NRST(NRST) (General)
J1PB14I/OMultiplexed I/O & Peripheral Pin PB14 (SPI, I2C)
J3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, I2C, ADC)
J5PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
J7VSSAGNDGround Reference Pin (VSSA)
J9NRSTISystem Enable & Hardware Reset (NRST)
K2PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, I2C, PWM)
K4PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC)
K6PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, ADC, DAC)
K8VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
L1VSSGNDGround Reference Pin (VSS)
L3VSSSMPSGNDGround Reference Pin (VSSSMPS)
L5PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC)
L7VSSGNDGround Reference Pin (VSS)
L9PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
M2VDD11PowerPower Supply Input (VDD11 — 3.3V VDD (Max 4.0V))
M4VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
M6PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, I2C, ADC)
M8PA3I/OMultiplexed I/O & Peripheral Pin PA3 (SPI, ADC)
N1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
N3VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
N5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C, RTC/CLK)
N7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
N9VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
P2VDD11PowerPower Supply Input (VDD11 — 3.3V VDD (Max 4.0V))
P4VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
P6PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
P8VSSGNDGround Reference Pin (VSS)
R1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
R3VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
R5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
R7PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
R9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
PIN A1 VDD
Power
Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 17 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32U375RGY6QTR (ST · WLCSP-68(3.1x3.2))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) - 2. Standard Pinout (Top View)
True package pinout (68 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) - 4. Package Dimensions (D×E×A)
WLCSP-68(3.1x3.2) · 3.20×3.10mm · Pitch 0.35mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) - 5. Recommended Land Pattern
IPC-7351B Footprint (68 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (17 figures · Page 1/2)
Showing 1–12 of 17 uncropped original figures for STM32U375
P55 · p55_fig02EXACT PACKAGE
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) — Figure 11. WLCSP52_SMPS ballout
Figure 11. WLCSP52_SMPS ballout
P59 · p59_fig01EXACT PACKAGE
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) — Figure 16. WLCSP68-Q_SMPS ballout
Figure 16. WLCSP68-Q_SMPS ballout
P60 · p60_fig01EXACT PACKAGE
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) — Figure 17. WLCSP68-G_SMPS ballout
Figure 17. WLCSP68-G_SMPS ballout
P190 · p190_fig01EXACT PACKAGE
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) — Figure 73. WLCSP52 - Outline
Figure 73. WLCSP52 - Outline
P1 · p01_fig011009×522px
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) — • 202000 SecureMark™-TLS
• 202000 SecureMark™-TLS
P55 · p55_fig011247×931px
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) — Figure 10. UFQFPN48 pinout
Figure 10. UFQFPN48 pinout
P55 · p55_fig01P55
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) — Datasheet Page 55 (p55_fig01)
Datasheet Page 55 (p55_fig01)
P85 · p85_fig011611×474px
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) — Figure 22. Pin loading conditions
Figure 22. Pin loading conditions
P85 · p85_fig01P85
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) — Datasheet Page 85 (p85_fig01)
Datasheet Page 85 (p85_fig01)
P86 · p86_fig011143×1520px
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) — Figure 24. STM32U375xx power supply scheme (without SMPS)
Figure 24. STM32U375xx power supply scheme (without SMPS)
P87 · p87_fig011488×1738px
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) — Figure 25. STM32U375xx power supply scheme (with SMPS)
Figure 25. STM32U375xx power supply scheme (with SMPS)
P150 · p150_fig01921×756px
STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) — Figure 39. ADC accuracy characteristics
Figure 39. ADC accuracy characteristics
Page 1 / 2 (17 extracted figures)

Technical Specifications & Part Details (STM32U375RGY6QTR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) is a 68-pin embedded microcontroller unit (mcu) featuring a 3.10 × 3.20 × 0.48 mm mechanical envelope (lead pitch e = 0.35 mm). Rated for 1.71 V to 3.6 V supply operation across -40 °C to +105 °C with integrated USB, UART, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40 °C to +105 °C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
48 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
31 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
3.10 × 3.20 × 0.48 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-68(3.1x3.2))
Pin Count & Lead PitchN / e
68 Pins | Pitch e = 0.35 mm (13.8 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3BOOT0 - (PH3)): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol68 auto-grouped pins
OK
IPC-7351B Land Pattern68 pads · Pitch 0.35mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-68(3.1x3.2))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.10 × 3.20 mm
Height (A) & Pitch (e)IPC-7351B
A=0.48mm · e=0.35mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
68P / 68Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-68(3.1x3.2)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32U375RGY6QTR (WLCSP-68(3.1x3.2))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32U375RGY6QTR (WLCSP-68(3.1x3.2))?

Manufactured by ST, the STM32U375RGY6QTR is housed in a WLCSP-68(3.1x3.2) package with 68 pins and a 0.35 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), A3 (PA15(JTDI): Multiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG)), A5 (PB5: Multiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C)), A7 (PB9: Multiplexed I/O & Peripheral Pin PB9 (SPI)), A9 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), B2 (VDDUSB: Power Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))).

What are the IPC-7351B PCB Footprint dimensions for STM32U375RGY6QTR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32U375RGY6QTR (WLCSP-68(3.1x3.2)) has a nominal body envelope of 3.20 × 3.10 mm, pitch e = 0.35 mm, and 68 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32U375RGY6QTR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32U375RGY6QTR (ST, WLCSP-68(3.1x3.2)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (68 pins) & STM32U375 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A3PA15(JTDI)Digital_IOSignal terminal PA15(JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_RTS. Supported peripheral buses: UART, SPI, SWD/JTAG.
A5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3. Supported peripheral buses: UART, SPI, I2C.
A7PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI.
A9VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B2VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B4PB3(JTDO/ TRACESWO)Digital_IOSignal terminal PB3(JTDO/ TRACESWO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA, SPI1SCK, SPI3. Supported peripheral buses: SPI, I2C, SWD/JTAG.
B6PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: SPI, I2C.
B8VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C1PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USB_DP. Supported peripheral buses: USB, UART, SPI.
C3PA14(JTCK/ SWCLK)Digital_IOSignal terminal PA14(JTCK/ SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SMBA, I2C1_SMBA, I2C3_SMBA. Supported peripheral buses: I2C, SWD/JTAG.
C5PH3BOOT0 - (PH3)Digital_IOSignal terminal PH3BOOT0 - (PH3) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH3BOOT0 - (PH3). Supported peripheral buses: I2C.
C7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C9PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
D2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D4PB4(NJTRST)Digital_IOSignal terminal PB4(NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA, SPI1_MISO. Supported peripheral buses: UART, SPI, I2C, SWD/JTAG.
D6VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D8IOD8Digital_IOGeneral Purpose Digital I/O Pin IOD8
E1PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USB_DM. Supported peripheral buses: USB, UART, SPI.
E3PA13(JTMS/ SWDIO)Digital_IOSignal terminal PA13(JTMS/ SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13(JTMS/ SWDIO). Supported peripheral buses: USB, SWD/JTAG.
E5PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
E7IOE7Digital_IOGeneral Purpose Digital I/O Pin IOE7
E9PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
F2PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: RTC/CLK.
F4PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: I2C, PWM.
F6PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
F8PH0OSC IN (- PH0)_Digital_IOSignal terminal PH0OSC IN (- PH0)_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0OSC IN (- PH0)_. Supported peripheral buses: RTC/CLK.
G1PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: PWM, RTC/CLK.
G3PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, RTC/CLK.
G5PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: SPI, I2C.
G7PH1 - OSC OUT (PH_1)Digital_IOSignal terminal PH1 - OSC OUT (PH_1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC OUT (PH_1). Supported peripheral buses: RTC/CLK.
G9PH0-OSC_INDigital_IOSignal terminal PH0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0-OSC_IN. Supported peripheral buses: RTC/CLK.
H2PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_DY_12TRACE. Supported peripheral buses: SPI, RTC/CLK.
H4PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_RDY_LPUART1TXOCTOS. Supported peripheral buses: SPI.
H6PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_RDY_UART4TXAUDIOCLK. Supported peripheral buses: UART, SPI.
H8NRST(NRST)Digital_IOSignal terminal NRST(NRST) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: NRST(NRST). Supported peripheral buses: General.
J1PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, I2C.
J3PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL, SPI1_MO, SPI1_IO2. Supported peripheral buses: SPI, I2C, ADC.
J5PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1. Supported peripheral buses: SPI, ADC, DAC, PWM.
J7VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
J9NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
K2PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL, SPI2_SCK. Supported peripheral buses: UART, SPI, I2C, PWM.
K4PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC.
K6PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: SPI, ADC, DAC.
K8VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
L1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
L3VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
L5PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC.
L7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
L9PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
M2VDD11Power_InPrimary positive power supply input (VDD11) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
M4VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
M6PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_. Supported peripheral buses: UART, SPI, I2C, ADC.
M8PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: SPI, ADC.
N1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
N3VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
N5PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCLOCTOSPI. Supported peripheral buses: I2C, RTC/CLK.
N7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
N9VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
P2VDD11Power_InPrimary positive power supply input (VDD11) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
P4VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
P6PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
P8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
R1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
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