![STM32N657I0H3Q (VFBGA-178) — Figure 8. VFBGA169 ballout [VFBGA-169(6x6)]](/api/v1/assets/C43080082/extracted/figures/p84_fig01.png)
![STM32N657I0H3Q (VFBGA-178) — Figure 68. VFBGA169 - Outline(13) [VFBGA-169(6x6)]](/api/v1/assets/C43080082/extracted/figures/p241_fig01.png)
![STM32N657I0H3Q (VFBGA-178) — Figure 7. VFBGA142 ballout [VFBGA-169(6x6)]](/api/v1/assets/C43080082/extracted/figures/p83_fig01.png)
![STM32N657I0H3Q (VFBGA-178) — Figure 74. VFBGA264 - Recommended footprint [VFBGA-169(6x6)]](/api/v1/assets/C43080082/extracted/figures/p255_fig01.png)
VFBGA-169(6x6) · 169P
Synchronized Pinout (Symbol / 2D / 3D) (178/178)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| A1 | PDR_ON | I/O | Multiplexed I/O & Peripheral Pin PDR_ON (General) |
| A2 | OTG2_HSDM | I/O | Multiplexed I/O & Peripheral Pin OTG2_HSDM (General) |
| A3 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| A4 | VDD33USB | Power | Power Supply Input (VDD33USB — 3.3V VDD (Max 4.0V)) |
| A5 | OTG1_HSDM | I/O | Multiplexed I/O & Peripheral Pin OTG1_HSDM (General) |
| A6 | UCPD1_CC1 | I/O | Multiplexed I/O & Peripheral Pin UCPD1_CC1 (General) |
| A7 | PH1OSC OUT(PH1) -_ | I/O | Multiplexed I/O & Peripheral Pin PH1OSC OUT(PH1) -_ (RTC/CLK) |
| A8 | PC6 | I/O | Multiplexed I/O & Peripheral Pin PC6 (UART, PWM) |
| A9 | PC7 | I/O | Multiplexed I/O & Peripheral Pin PC7 (General) |
| A10 | PE6 | I/O | Multiplexed I/O & Peripheral Pin PE6 (UART, I2C, PWM) |
| A11 | PD6 | I/O | Multiplexed I/O & Peripheral Pin PD6 (SPI) |
| A12 | PD0 | I/O | Multiplexed I/O & Peripheral Pin PD0 (UART) |
| A13 | PD3 | I/O | Multiplexed I/O & Peripheral Pin PD3 (UART, I2C) |
| A14 | VSS | GND | Ground Reference Pin (VSS) |
| B1 | IOB1 | I/O | General Purpose Digital I/O Pin IOB1 |
| B2 | OTG2_HSDP | I/O | Multiplexed I/O & Peripheral Pin OTG2_HSDP (General) |
| B3 | OTG1_ID | I/O | Multiplexed I/O & Peripheral Pin OTG1_ID (General) |
| B4 | OTG2_TXRTUNE | I/O | Multiplexed I/O & Peripheral Pin OTG2_TXRTUNE (General) |
| B5 | OTG1_HSDP | I/O | Multiplexed I/O & Peripheral Pin OTG1_HSDP (General) |
| B6 | UCPD1_CC2 | I/O | Multiplexed I/O & Peripheral Pin UCPD1_CC2 (General) |
| B7 | PH0OSC IN(PH0) -_ | I/O | Multiplexed I/O & Peripheral Pin PH0OSC IN(PH0) -_ (RTC/CLK) |
| B8 | PC1 | I/O | Multiplexed I/O & Peripheral Pin PC1 (UART, SPI, PWM) |
| B9 | PE11 | I/O | Multiplexed I/O & Peripheral Pin PE11 (General) |
| B10 | PE15 | I/O | Multiplexed I/O & Peripheral Pin PE15 (UART, SPI) |
| B11 | PD7 | I/O | Multiplexed I/O & Peripheral Pin PD7 (SPI, PWM) |
| B12 | PD1 | I/O | Multiplexed I/O & Peripheral Pin PD1 (UART) |
| B13 | PD4 | I/O | Multiplexed I/O & Peripheral Pin PD4 (UART, I2C) |
| B14 | PE9 | I/O | Multiplexed I/O & Peripheral Pin PE9 (General) |
| C1 | IOC1 | I/O | General Purpose Digital I/O Pin IOC1 |
| C2 | VBAT | Power | Power Supply Input (VBAT — 3.3V VDD (Max 4.0V)) |
| C3 | PC13 | I/O | Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK) |
| C4 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| C5 | OTG2_ID | I/O | Multiplexed I/O & Peripheral Pin OTG2_ID (General) |
| C6 | PC8 | I/O | Multiplexed I/O & Peripheral Pin PC8 (UART, I2C) |
| C7 | PC11 | I/O | Multiplexed I/O & Peripheral Pin PC11 (UART, SPI, I2C) |
| C8 | PH9 | I/O | Multiplexed I/O & Peripheral Pin PH9 (I2C, PWM) |
| C9 | PE14 | I/O | Multiplexed I/O & Peripheral Pin PE14 (SPI, I2C) |
| C10 | PE13 | I/O | Multiplexed I/O & Peripheral Pin PE13 (I2C) |
| C11 | PD10 | I/O | Multiplexed I/O & Peripheral Pin PD10 (General) |
| C12 | PD15 | I/O | Multiplexed I/O & Peripheral Pin PD15 (UART, I2C) |
| C13 | PE8 | I/O | Multiplexed I/O & Peripheral Pin PE8 (UART) |
| C14 | PE10 | I/O | Multiplexed I/O & Peripheral Pin PE10 (UART) |
| D1 | V08CAP | I/O | Multiplexed I/O & Peripheral Pin V08CAP (General) |
| D2 | VFBSMPS | I/O | Multiplexed I/O & Peripheral Pin VFBSMPS (General) |
| D3 | BOOT0 | I | Input-Only Pin BOOT0 (General) |
| D4 | VDDA18USB | Power | Power Supply Input (VDDA18USB — 3.3V VDD (Max 4.0V)) |
| D5 | OTG1_TXRTUNE | I/O | Multiplexed I/O & Peripheral Pin OTG1_TXRTUNE (General) |
| D6 | PC9 | I/O | Multiplexed I/O & Peripheral Pin PC9 (UART, I2C, RTC/CLK) |
| D7 | PC12 | I/O | Multiplexed I/O & Peripheral Pin PC12 (UART, SPI) |
| D8 | PC10 | I/O | Multiplexed I/O & Peripheral Pin PC10 (UART, SPI, I2C) |
| D9 | PE5 | I/O | Multiplexed I/O & Peripheral Pin PE5 (UART, I2C, PWM) |
| D10 | PE12 | I/O | Multiplexed I/O & Peripheral Pin PE12 (SPI) |
| D11 | PE7 | I/O | Multiplexed I/O & Peripheral Pin PE7 (General) |
| D12 | PD14 | I/O | Multiplexed I/O & Peripheral Pin PD14 (UART, I2C) |
| D13 | PD8 | I/O | Multiplexed I/O & Peripheral Pin PD8 (UART) |
| D14 | PD5 | I/O | Multiplexed I/O & Peripheral Pin PD5 (PWM) |
| E1 | VDDA18PMU | Power | Power Supply Input (VDDA18PMU — 3.3V VDD (Max 4.0V)) |
| E2 | VSSAPMU | GND | Ground Reference Pin (VSSAPMU) |
| E3 | PWR_ON | I/O | Multiplexed I/O & Peripheral Pin PWR_ON (General) |
| E4 | NRST | I | System Enable & Hardware Reset (NRST) |
| E5 | VDDA18AON | Power | Power Supply Input (VDDA18AON — 3.3V VDD (Max 4.0V)) |
| E6 | PH2 | I/O | Multiplexed I/O & Peripheral Pin PH2 (UART) |
| E7 | VSS | GND | Ground Reference Pin (VSS) |
| E8 | VDDIO4 | Power | Power Supply Input (VDDIO4 — 3.3V VDD (Max 4.0V)) |
| E9 | VDDIO4 | Power | Power Supply Input (VDDIO4 — 3.3V VDD (Max 4.0V)) |
| E10 | PD2 | I/O | Multiplexed I/O & Peripheral Pin PD2 (SPI) |
| E11 | PD12 | I/O | Multiplexed I/O & Peripheral Pin PD12 (General) |
| E12 | PB3 | I/O | Multiplexed I/O & Peripheral Pin PB3 (UART) |
| E13 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (SPI, RTC/CLK) |
| E14 | PD13 | I/O | Multiplexed I/O & Peripheral Pin PD13 (UART, SPI, PWM) |
| F1 | VSSSMPS | GND | Ground Reference Pin (VSSSMPS) |
| F2 | VSSSMPS | GND | Ground Reference Pin (VSSSMPS) |
| F3 | VSSSMPS | GND | Ground Reference Pin (VSSSMPS) |
| F4 | VSSSMPS | GND | Ground Reference Pin (VSSSMPS) |
| F5 | VSSAON | GND | Ground Reference Pin (VSSAON) |
| F10 | VSS | GND | Ground Reference Pin (VSS) |
| F11 | PD11 | I/O | Multiplexed I/O & Peripheral Pin PD11 (SPI, I2C) |
| F12 | PE0 | I/O | Multiplexed I/O & Peripheral Pin PE0 (UART) |
| F13 | PE1 | I/O | Multiplexed I/O & Peripheral Pin PE1 (UART) |
| F14 | PE2 | I/O | Multiplexed I/O & Peripheral Pin PE2 (General) |
| G1 | VLXSMPS | I/O | Multiplexed I/O & Peripheral Pin VLXSMPS (General) |
| G2 | VLXSMPS | I/O | Multiplexed I/O & Peripheral Pin VLXSMPS (General) |
| G3 | VLXSMPS | I/O | Multiplexed I/O & Peripheral Pin VLXSMPS (General) |
| G4 | VLXSMPS | I/O | Multiplexed I/O & Peripheral Pin VLXSMPS (General) |
| G10 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| G11 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| G12 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| G13 | PE3 | I/O | Multiplexed I/O & Peripheral Pin PE3 (General) |
| G14 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (SPI) |
| H1 | VDDSMPS | Power | Power Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V)) |
| H2 | VDDSMPS | Power | Power Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V)) |
| H3 | VDDSMPS | Power | Power Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V)) |
| H4 | VDDSMPS | Power | Power Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V)) |
| H10 | VSS | GND | Ground Reference Pin (VSS) |
| H11 | VSS | GND | Ground Reference Pin (VSS) |
| H12 | PD9 | I/O | Multiplexed I/O & Peripheral Pin PD9 (UART) |
| H13 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (SPI) |
| H14 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (SPI) |
| J1 | PF4 | I/O | Multiplexed I/O & Peripheral Pin PF4 (SPI, ADC) |
| J2 | PF6 | I/O | Multiplexed I/O & Peripheral Pin PF6 (UART, SPI, ADC, PWM) |
| J3 | PF10 | I/O | Multiplexed I/O & Peripheral Pin PF10 (General) |
| J4 | PF5 | I/O | Multiplexed I/O & Peripheral Pin PF5 (UART, SPI) |
| J5 | PF3 | I/O | Multiplexed I/O & Peripheral Pin PF3 (ADC) |
| J10 | VDDIO3 | Power | Power Supply Input (VDDIO3 — 3.3V VDD (Max 4.0V)) |
| J11 | VDDIO3 | Power | Power Supply Input (VDDIO3 — 3.3V VDD (Max 4.0V)) |
| J12 | PN12 | I/O | Multiplexed I/O & Peripheral Pin PN12 (General) |
| J13 | PN4 | I/O | Multiplexed I/O & Peripheral Pin PN4 (General) |
| J14 | PN8 | I/O | Multiplexed I/O & Peripheral Pin PN8 (General) |
| K1 | PF2 | I/O | Multiplexed I/O & Peripheral Pin PF2 (UART, SPI) |
| K2 | PF14 | I/O | Multiplexed I/O & Peripheral Pin PF14 (UART, ADC) |
| K3 | PF15 | I/O | Multiplexed I/O & Peripheral Pin PF15 (UART) |
| K4 | PF7 | I/O | Multiplexed I/O & Peripheral Pin PF7 (SPI, ADC, PWM) |
| K5 | VSS | GND | Ground Reference Pin (VSS) |
| K6 | VDDCORE | Power | Power Supply Input (VDDCORE — 3.3V VDD (Max 4.0V)) |
| K7 | VDDCORE | Power | Power Supply Input (VDDCORE — 3.3V VDD (Max 4.0V)) |
| K8 | VDDCORE | Power | Power Supply Input (VDDCORE — 3.3V VDD (Max 4.0V)) |
| K9 | VDDCORE | Power | Power Supply Input (VDDCORE — 3.3V VDD (Max 4.0V)) |
| K10 | VSS | GND | Ground Reference Pin (VSS) |
| K11 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (UART, SPI) |
| K12 | PN6 | I/O | Multiplexed I/O & Peripheral Pin PN6 (General) |
| K13 | PN7 | I/O | Multiplexed I/O & Peripheral Pin PN7 (General) |
| K14 | PN5 | I/O | Multiplexed I/O & Peripheral Pin PN5 (General) |
| L1 | PF8 | I/O | Multiplexed I/O & Peripheral Pin PF8 (UART) |
| L2 | PF11 | I/O | Multiplexed I/O & Peripheral Pin PF11 (SPI, ADC) |
| L3 | PF12 | I/O | Multiplexed I/O & Peripheral Pin PF12 (UART, ADC) |
| L4 | VDDA18PLL | Power | Power Supply Input (VDDA18PLL — 3.3V VDD (Max 4.0V)) |
| L5 | PG14 | I/O | Multiplexed I/O & Peripheral Pin PG14 (UART, SPI) |
| L6 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (UART, SPI, ADC) |
| L7 | VDDCORE | Power | Power Supply Input (VDDCORE — 3.3V VDD (Max 4.0V)) |
| L8 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (SPI, I2C, ADC) |
| L9 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM) |
| L10 | PB11 | I/O | Multiplexed I/O & Peripheral Pin PB11 (UART, I2C, ADC) |
| L11 | PB4 (NJTRST) | I/O | Multiplexed I/O & Peripheral Pin PB4 (NJTRST) (UART, SPI, SWD/JTAG) |
| L12 | PG8 | I/O | Multiplexed I/O & Peripheral Pin PG8 (UART, SPI, PWM, RTC/CLK) |
| L13 | PN2 | I/O | Multiplexed I/O & Peripheral Pin PN2 (General) |
| L14 | PN9 | I/O | Multiplexed I/O & Peripheral Pin PN9 (General) |
| M1 | VREF+ | Analog | Multiplexed I/O & Peripheral Pin VREF+ (General) |
| M2 | PF13 | I/O | Multiplexed I/O & Peripheral Pin PF13 (UART, ADC) |
| M3 | VDDA18ADC | Power | Power Supply Input (VDDA18ADC — 3.3V VDD (Max 4.0V)) |
| M4 | VSSA | GND | Ground Reference Pin (VSSA) |
| M5 | PG15 | I/O | Multiplexed I/O & Peripheral Pin PG15 (SPI, ADC) |
| M6 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (UART, SPI, ADC) |
| M7 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (SPI, I2C, ADC) |
| M8 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (SPI, I2C, ADC, PWM) |
| M9 | PG1 | I/O | Multiplexed I/O & Peripheral Pin PG1 (UART, SPI) |
| M10 | PB12 | I/O | Multiplexed I/O & Peripheral Pin PB12 (UART, SPI) |
| M11 | PB5 (JTDO/TRACESWO) | I/O | Multiplexed I/O & Peripheral Pin PB5 (JTDO/TRACESWO) (SPI, SWD/JTAG) |
| M12 | PG0 | I/O | Multiplexed I/O & Peripheral Pin PG0 (General) |
| M13 | PN0 | I/O | Multiplexed I/O & Peripheral Pin PN0 (General) |
| M14 | PN10 | I/O | Multiplexed I/O & Peripheral Pin PN10 (General) |
| N1 | VREF - | Analog | Multiplexed I/O & Peripheral Pin VREF - (General) |
| N2 | CSI_D1N | I/O | Multiplexed I/O & Peripheral Pin CSI_D1N (General) |
| N3 | CSI_CKN | I/O | Multiplexed I/O & Peripheral Pin CSI_CKN (General) |
| N4 | CSI_D0N | I/O | Multiplexed I/O & Peripheral Pin CSI_D0N (General) |
| N5 | CSI_REXT | I/O | Multiplexed I/O & Peripheral Pin CSI_REXT (General) |
| N6 | VDDCSI | Power | Power Supply Input (VDDCSI — 3.3V VDD (Max 4.0V)) |
| N7 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (UART, ADC, PWM) |
| N8 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM) |
| N9 | PG12 | I/O | Multiplexed I/O & Peripheral Pin PG12 (UART, SPI) |
| N10 | PG10 | I/O | Multiplexed I/O & Peripheral Pin PG10 (UART, SPI) |
| N11 | PG2 | I/O | Multiplexed I/O & Peripheral Pin PG2 (UART, SPI) |
| N12 | PA15(JTDI) | I/O | Multiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG) |
| N13 | PN3 | I/O | Multiplexed I/O & Peripheral Pin PN3 (General) |
| N14 | PN11 | I/O | Multiplexed I/O & Peripheral Pin PN11 (General) |
| P1 | VSS | GND | Ground Reference Pin (VSS) |
| P2 | CSI_D1P | I/O | Multiplexed I/O & Peripheral Pin CSI_D1P (General) |
| P3 | CSI_CKP | I/O | Multiplexed I/O & Peripheral Pin CSI_CKP (General) |
| P4 | CSI_D0P | I/O | Multiplexed I/O & Peripheral Pin CSI_D0P (General) |
| P5 | VDDA18CSI | Power | Power Supply Input (VDDA18CSI — 3.3V VDD (Max 4.0V)) |
| P6 | PA14(JTCK/SWCLK) | I/O | Multiplexed I/O & Peripheral Pin PA14(JTCK/SWCLK) (SWD/JTAG) |
| P7 | PA13(JTMS/SWDIO) | I/O | Multiplexed I/O & Peripheral Pin PA13(JTMS/SWDIO) (SWD/JTAG) |
| P8 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (UART, I2C, ADC, RTC/CLK) |
| P9 | PG13 | I/O | Multiplexed I/O & Peripheral Pin PG13 (UART, PWM) |
| P10 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM) |
| P11 | PB10 | I/O | Multiplexed I/O & Peripheral Pin PB10 (SPI, I2C, ADC) |
| P12 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (UART, SPI, ADC) |
| P13 | PN1 | I/O | Multiplexed I/O & Peripheral Pin PN1 (General) |
| P14 | VSS | GND | Ground Reference Pin (VSS) |
PIN A1 PDR_ON
I/OMultiplexed I/O & Peripheral Pin PDR_ON (General)
Design note: Signal terminal PDR_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (178 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
VFBGA-178 · 12.00×12.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (178 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for STM32N657
P229 · p229_fig01EXACT PACKAGE
P22 · p22_fig011751×849px
P79 · p79_fig011752×1837px
P133 · p133_fig011875×2397px
P148 · p148_fig011546×467px
P189 · p189_fig011546×981px
P189 · p189_fig021546×750px
P240 · p240_fig011752×1356px
P84 · p84_fig01EXACT PACKAGE
P241 · p241_fig01EXACT PACKAGE
P83 · p83_fig011752×1837px
P255 · p255_fig011752×1356px
Technical Specifications & Part Details (STM32N657I0H3Q)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32N657I0H3Q (VFBGA-178) is a 178-pin embedded microcontroller unit (mcu) featuring a 12.00 × 12.00 × 0.85 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
800 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
12.00 × 12.00 × 0.85 mm (A1=0.22 mm)
Package family: BGA (VFBGA-178)
Pin Count & Lead PitchN / e
178 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PA6): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol178 auto-grouped pins
IPC-7351B Land Pattern178 pads · Pitch 0.80mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32N657 (2)
VFBGA-178 · 178P
Mechanical Dimensions & Land Pattern (VFBGA-178)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
12.00 × 12.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.80mm
Pad Size (W × L)Level B
0.38 × 0.38 mm
Pins / Total PadsTopology
178P / 178Pad (BGA_GRID)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit VFBGA-178 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32N657I0H3Q (VFBGA-178)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32N657I0H3Q (VFBGA-178)?
Manufactured by ST, the STM32N657I0H3Q is housed in a VFBGA-178 package with 178 pins and a 0.80 mm lead pitch. Key pins include: A1 (PDR_ON: Multiplexed I/O & Peripheral Pin PDR_ON (General)), A2 (OTG2_HSDM: Multiplexed I/O & Peripheral Pin OTG2_HSDM (General)), A3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), A4 (VDD33USB: Power Supply Input (VDD33USB — 3.3V VDD (Max 4.0V))), A5 (OTG1_HSDM: Multiplexed I/O & Peripheral Pin OTG1_HSDM (General)), A6 (UCPD1_CC1: Multiplexed I/O & Peripheral Pin UCPD1_CC1 (General)).
What are the IPC-7351B PCB Footprint dimensions for STM32N657I0H3Q?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32N657I0H3Q (VFBGA-178) has a nominal body envelope of 12.00 × 12.00 mm, pitch e = 0.80 mm, and 178 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32N657I0H3Q?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32N657I0H3Q (ST, VFBGA-178) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (178 pins) & STM32N657 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| A1 | PDR_ON | Digital_IO | Signal terminal PDR_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General. |
| A2 | OTG2_HSDM | Digital_IO | Signal terminal OTG2_HSDM (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG2_HSDM. Supported peripheral buses: General. |
| A3 | NC | NC | Signal terminal NC (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| A4 | VDD33USB | Power_In | Primary positive power supply input (VDD33USB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| A5 | OTG1_HSDM | Digital_IO | Signal terminal OTG1_HSDM (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG1_HSDM. Supported peripheral buses: General. |
| A6 | UCPD1_CC1 | Digital_IO | Signal terminal UCPD1_CC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: UCPD1_CC1. Supported peripheral buses: General. |
| A7 | PH1OSC OUT(PH1) -_ | Digital_IO | Signal terminal PH1OSC OUT(PH1) -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1OSC OUT(PH1) -_. Supported peripheral buses: RTC/CLK. |
| A8 | PC6 | Digital_IO | Signal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: UART, PWM. |
| A9 | PC7 | Digital_IO | Signal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General. |
| A10 | PE6 | Digital_IO | Signal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C, PWM. |
| A11 | PD6 | Digital_IO | Signal terminal PD6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI. |
| A12 | PD0 | Digital_IO | Signal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: UART. |
| A13 | PD3 | Digital_IO | Signal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SMBA. Supported peripheral buses: UART, I2C. |
| A14 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| B1 | IOB1 | Digital_IO | General Purpose Digital I/O Pin IOB1 |
| B2 | OTG2_HSDP | Digital_IO | Signal terminal OTG2_HSDP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG2_HSDP. Supported peripheral buses: General. |
| B3 | OTG1_ID | Digital_IO | Signal terminal OTG1_ID (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG1_ID. Supported peripheral buses: General. |
| B4 | OTG2_TXRTUNE | Digital_IO | Signal terminal OTG2_TXRTUNE (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG2_TXRTUNE. Supported peripheral buses: General. |
| B5 | OTG1_HSDP | Digital_IO | Signal terminal OTG1_HSDP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG1_HSDP. Supported peripheral buses: General. |
| B6 | UCPD1_CC2 | Digital_IO | Signal terminal UCPD1_CC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: UCPD1_CC2. Supported peripheral buses: General. |
| B7 | PH0OSC IN(PH0) -_ | Digital_IO | Signal terminal PH0OSC IN(PH0) -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0OSC IN(PH0) -_. Supported peripheral buses: RTC/CLK. |
| B8 | PC1 | Digital_IO | Signal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI, PWM. |
| B9 | PE11 | Digital_IO | Signal terminal PE11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE11. Supported peripheral buses: General. |
| B10 | PE15 | Digital_IO | Signal terminal PE15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI5_SCK. Supported peripheral buses: UART, SPI. |
| B11 | PD7 | Digital_IO | Signal terminal PD7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MOSI, SPI3_NSS. Supported peripheral buses: SPI, PWM. |
| B12 | PD1 | Digital_IO | Signal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: UART. |
| B13 | PD4 | Digital_IO | Signal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: UART, I2C. |
| B14 | PE9 | Digital_IO | Signal terminal PE9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE9. Supported peripheral buses: General. |
| C1 | IOC1 | Digital_IO | General Purpose Digital I/O Pin IOC1 |
| C2 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| C3 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| C4 | NC | NC | Signal terminal NC (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| C5 | OTG2_ID | Digital_IO | Signal terminal OTG2_ID (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG2_ID. Supported peripheral buses: General. |
| C6 | PC8 | Digital_IO | Signal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C3_SMBA. Supported peripheral buses: UART, I2C. |
| C7 | PC11 | Digital_IO | Signal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C4_SDA, SPI3_MISO. Supported peripheral buses: UART, SPI, I2C. |
| C8 | PH9 | Digital_IO | Signal terminal PH9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C, PWM. |
| C9 | PE14 | Digital_IO | Signal terminal PE14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C4_SDA, SPI4_MOSI_SAI2MCLKB. Supported peripheral buses: SPI, I2C. |
| C10 | PE13 | Digital_IO | Signal terminal PE13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE13. Supported peripheral buses: I2C. |
| C11 | PD10 | Digital_IO | Signal terminal PD10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General. |
| C12 | PD15 | Digital_IO | Signal terminal PD15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: UART, I2C. |
| C13 | PE8 | Digital_IO | Signal terminal PE8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: UART. |
| C14 | PE10 | Digital_IO | Signal terminal PE10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE10. Supported peripheral buses: UART. |
| D1 | V08CAP | Digital_IO | Signal terminal V08CAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: V08CAP. Supported peripheral buses: General. |
| D2 | VFBSMPS | Digital_IO | Signal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General. |
| D3 | BOOT0 | Digital_IO | Signal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General. |
| D4 | VDDA18USB | Power_In | Primary positive power supply input (VDDA18USB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| D5 | OTG1_TXRTUNE | Digital_IO | Signal terminal OTG1_TXRTUNE (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OTG1_TXRTUNE. Supported peripheral buses: General. |
| D6 | PC9 | Digital_IO | Signal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C3_SDA. Supported peripheral buses: UART, I2C, RTC/CLK. |
| D7 | PC12 | Digital_IO | Signal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI6_SCK, SPI3_MOSI. Supported peripheral buses: UART, SPI. |
| D8 | PC10 | Digital_IO | Signal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI, I2C. |
| D9 | PE5 | Digital_IO | Signal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C, PWM. |
| D10 | PE12 | Digital_IO | Signal terminal PE12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE12. Supported peripheral buses: SPI. |
| D11 | PE7 | Digital_IO | Signal terminal PE7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General. |
| D12 | PD14 | Digital_IO | Signal terminal PD14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: UART, I2C. |
| D13 | PD8 | Digital_IO | Signal terminal PD8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD8. Supported peripheral buses: UART. |
| D14 | PD5 | Digital_IO | Signal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: PWM. |
| E1 | VDDA18PMU | Power_In | Primary positive power supply input (VDDA18PMU) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| E2 | VSSAPMU | GND | 0V electrical ground return terminal (VSSAPMU) for internal core logic, I/O drivers, and analog sub-blocks. |
| E3 | PWR_ON | Digital_IO | Signal terminal PWR_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PWR_ON. Supported peripheral buses: General. |
| E4 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| E5 | VDDA18AON | Power_In | Primary positive power supply input (VDDA18AON) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| E6 | PH2 | Digital_IO | Signal terminal PH2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH2. Supported peripheral buses: UART. |
| E7 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| E8 | VDDIO4 | Power_In | Primary positive power supply input (VDDIO4) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |