ChipDocs.org
⌘K
2284 PARTSUpload PDF
STM32WB55VEQ7 (UFBGA-129) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32WB55VEQ7

STID: C3215575UFBGA-129 · 129 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32WB55VEQ7 (UFBGA-129)A1PE1A2PB6A3PB5A6PD5A7PD10A8VDD_DCAP4A11PA13 (JTMS SA12VDDUSBA13PA12B1PE2B2PE0B3PB4 (NJTRST)B4PD12B5PD11B6PD8B7PD2B8VSS_DCAP4B9PC10B10PC12B11PD0B12VSSB13PA11C1PD13C2PD15C3PB7C4PB3 (JTDO)C5PD7C6PD4C7PD1C8PC11C9PA15 (JTDI)C10PA14 (JTCK SC11VSSC12PA10C13PC9D2VBATD3PD14D4PD9D6PD6D8PD3D10PC6D11PC8D12PC7E2PC15 - OSC32E3PC14 - OSC32E5VSSE7VSSE9VSSE11PB14E12PB13F1PH0F2VDD_DCAP1F3VSS_DCAP1F4PC13F6VDDF8VDDF10PB15F11VLXSMPSF12VDDSMPSF13VDDSMPSG1PH3 BOOT0 -G2PH1G3PB8G5VSSG7VDDN13OSC_OUTN12VDDRFN11VSSRFN8VSSRFN7VDD_DCAP2N6PB2N3PA7N2PA5N1PA2M13OSC_INM12VSSRFM11VSSRFM10VSSRFM9RF1M8VSSRFM7VSS_DCAP2M6PB11M5PC4M4PA8M3PA6M2PA3M1PA0L13PB0L12PB1L11VSSRFL10VSSRFL9VSSRFL8VSSRFL7VSSRFL6PB10L5PC5L4PA9L3PA4L2PA1L1VREF+K12AT1K11AT0K10VSSRFK8VSSRFK6VSSK4VSSK3VDDAK2VSSAJ12VDD_DCAP3J11VSS_DCAP3J9VSSJ7VSSJ5VSSJ3PC3J2PC2H13PE4H12PE3H11VFBSMPSH10PB12H8VDDH6VDDH4PB9H3PC0H2NRSTH1PC1G13VSSSMPSG12VSSSMPSG11VLXSMPSG9VSSGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.888.983.878.773.768.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6-73.7-78.7-83.8-88.9mm
2. 2D FOOTPRINT
A1A2A3A6A7A11A12A13B1B2B3B4B5B6B7B8B9B10B11B12B13C1C2C3C4C5C6C7C8C9C10C11C12C13D2D3D4D6D8D10D11D12E2E3E5E7E9E11E12F1F2F3F4F6F8F10F11F12F13G1G2G3G5G7G9G11G12G13H1H2H3H4H6H8H10H11H12H13J2J3J5J7J9J11J12K2K3K4K6K8K10K11K12L1L2L3L4L5L6L7L8L9L10L11L12L13M1M2M3M4M5M6M7M8M9M10M11M12M13N1N2N3N6N7N8N11N12N13A8E=7.00mm · Pitch e=0.50mmD=7.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (129/129)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
A2PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART)
A3PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI)
A6PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
A7PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
A8VDD_DCAP4PowerPower Supply Input (VDD_DCAP4 — 3.3V VDD (Max 4.0V))
A11PA13 (JTMS SWDIO)_I/OMultiplexed I/O & Peripheral Pin PA13 (JTMS SWDIO)_ (USB, SWD/JTAG)
A12VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
A13PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART)
B1PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
B2PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
B3PB4 (NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4 (NJTRST) (SPI, I2C, SWD/JTAG)
B4PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
B5PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
B6PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
B7PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
B8VSS_DCAP4GNDGround Reference Pin (VSS_DCAP4)
B9PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
B10PC12I/OMultiplexed I/O & Peripheral Pin PC12 (RTC/CLK)
B11PD0I/OMultiplexed I/O & Peripheral Pin PD0 (SPI)
B12VSSGNDGround Reference Pin (VSS)
B13PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, SPI, PWM)
C1PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
C2PD15I/OMultiplexed I/O & Peripheral Pin PD15 (PWM)
C3PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
C4PB3 (JTDO)I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO) (UART, PWM, SWD/JTAG)
C5PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
C6PD4I/OMultiplexed I/O & Peripheral Pin PD4 (SPI)
C7PD1I/OMultiplexed I/O & Peripheral Pin PD1 (SPI)
C8PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
C9PA15 (JTDI)I/OMultiplexed I/O & Peripheral Pin PA15 (JTDI) (SPI, SWD/JTAG)
C10PA14 (JTCK SWCLK)_I/OMultiplexed I/O & Peripheral Pin PA14 (JTCK SWCLK)_ (I2C, SWD/JTAG)
C11VSSGNDGround Reference Pin (VSS)
C12PA10I/OMultiplexed I/O & Peripheral Pin PA10 (USB, I2C)
C13PC9I/OMultiplexed I/O & Peripheral Pin PC9 (USB, SPI)
D2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
D3PD14I/OMultiplexed I/O & Peripheral Pin PD14 (PWM)
D4PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
D6PD6I/OMultiplexed I/O & Peripheral Pin PD6 (I2C)
D8PD3I/OMultiplexed I/O & Peripheral Pin PD3 (SPI)
D10PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
D11PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
D12PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
E2PC15 - OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK)
E3PC14 - OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK)
E5VSSGNDGround Reference Pin (VSS)
E7VSSGNDGround Reference Pin (VSS)
E9VSSGNDGround Reference Pin (VSS)
E11PB14I/OMultiplexed I/O & Peripheral Pin PB14 (SPI, PWM)
E12PB13I/OMultiplexed I/O & Peripheral Pin PB13 (SPI, PWM)
F1PH0I/OMultiplexed I/O & Peripheral Pin PH0 (General)
F2VDD_DCAP1PowerPower Supply Input (VDD_DCAP1 — 3.3V VDD (Max 4.0V))
F3VSS_DCAP1GNDGround Reference Pin (VSS_DCAP1)
F4PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
F6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F10PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, RTC/CLK)
F11VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
F12VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
F13VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
G1PH3 BOOT0 -I/OMultiplexed I/O & Peripheral Pin PH3 BOOT0 - (General)
G2PH1I/OMultiplexed I/O & Peripheral Pin PH1 (General)
G3PB8I/OMultiplexed I/O & Peripheral Pin PB8 (PWM)
G5VSSGNDGround Reference Pin (VSS)
G7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G9VSSGNDGround Reference Pin (VSS)
G11VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
G12VSSSMPSGNDGround Reference Pin (VSSSMPS)
G13VSSSMPSGNDGround Reference Pin (VSSSMPS)
H1PC1I/OMultiplexed I/O & Peripheral Pin PC1 (I2C, ADC)
H2NRSTISystem Enable & Hardware Reset (NRST)
H3PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
H4PB9I/OMultiplexed I/O & Peripheral Pin PB9 (I2C)
H6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
H8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
H10PB12I/OMultiplexed I/O & Peripheral Pin PB12 (SPI)
H11VFBSMPSI/OMultiplexed I/O & Peripheral Pin VFBSMPS (General)
H12PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
H13PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
J2PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
J3PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
J5VSSGNDGround Reference Pin (VSS)
J7VSSGNDGround Reference Pin (VSS)
J9VSSGNDGround Reference Pin (VSS)
J11VSS_DCAP3GNDGround Reference Pin (VSS_DCAP3)
J12VDD_DCAP3PowerPower Supply Input (VDD_DCAP3 — 3.3V VDD (Max 4.0V))
K2VSSAGNDGround Reference Pin (VSSA)
K3VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
K4VSSGNDGround Reference Pin (VSS)
K6VSSGNDGround Reference Pin (VSS)
K8VSSRFGNDGround Reference Pin (VSSRF)
K10VSSRFGNDGround Reference Pin (VSSRF)
K11AT0I/OMultiplexed I/O & Peripheral Pin AT0 (General)
K12AT1I/OMultiplexed I/O & Peripheral Pin AT1 (General)
L1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
L2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (SPI, PWM)
L3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI)
L4PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C)
L5PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
L6PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, PWM)
L7VSSRFGNDGround Reference Pin (VSSRF)
L8VSSRFGNDGround Reference Pin (VSSRF)
L9VSSRFGNDGround Reference Pin (VSSRF)
L10VSSRFGNDGround Reference Pin (VSSRF)
L11VSSRFGNDGround Reference Pin (VSSRF)
L12PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART)
L13PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
M1PA0I/OMultiplexed I/O & Peripheral Pin PA0 (PWM, RTC/CLK)
M2PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
M3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, ADC)
M4PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, SPI, ADC, RTC/CLK)
M5PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
M6PB11I/OMultiplexed I/O & Peripheral Pin PB11 (PWM)
M7VSS_DCAP2GNDGround Reference Pin (VSS_DCAP2)
M8VSSRFGNDGround Reference Pin (VSSRF)
M9RF1I/OMultiplexed I/O & Peripheral Pin RF1 (General)
M10VSSRFGNDGround Reference Pin (VSSRF)
M11VSSRFGNDGround Reference Pin (VSSRF)
M12VSSRFGNDGround Reference Pin (VSSRF)
M13OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
N1PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
N2PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, PWM)
N3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
N6PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C, RTC/CLK)
N7VDD_DCAP2PowerPower Supply Input (VDD_DCAP2 — 3.3V VDD (Max 4.0V))
N8VSSRFGNDGround Reference Pin (VSSRF)
N11VSSRFGNDGround Reference Pin (VSSRF)
N12VDDRFPowerPower Supply Input (VDDRF — 3.3V VDD (Max 4.0V))
N13OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
PIN A1 PE1
I/O
Multiplexed I/O & Peripheral Pin PE1 (General)
Design note: Alt: TSC G7_IO2LCDSEG37_ ,_ , TIM17_CH1 , CM4_EVENTOUT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32WB55VEQ7 (ST · UFBGA-129)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32WB55VEQ7 (UFBGA-129) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32WB55VEQ7 (UFBGA-129) - 2. Standard Pinout (Top View)
True package pinout (129 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32WB55VEQ7 (UFBGA-129) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32WB55VEQ7 (UFBGA-129) - 4. Package Dimensions (D×E×A)
UFBGA-129 · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32WB55VEQ7 (UFBGA-129) - 5. Recommended Land Pattern
IPC-7351B Footprint (129 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32WB55VEQ7 (UFBGA-129) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for STM32WB55 / STM32WB35
P59 · p59_fig01EXACT PACKAGE
STM32WB55VEQ7 (UFBGA-129) — Figure 12. STM32WB55Vx WLCSP100 ballout(1)
Figure 12. STM32WB55Vx WLCSP100 ballout(1)
P59 · p59_fig02EXACT PACKAGE
STM32WB55VEQ7 (UFBGA-129) — Figure 13. STM32WB55Vx UFBGA129 ballout(1)
Figure 13. STM32WB55Vx UFBGA129 ballout(1)
P82 · p82_fig01EXACT PACKAGE
STM32WB55VEQ7 (UFBGA-129) — Figure 16. Power supply scheme (all packages except UFBGA129 and WLCSP100)
Figure 16. Power supply scheme (all packages except UFBGA129 and WLCSP100)
P83 · p83_fig01EXACT PACKAGE
STM32WB55VEQ7 (UFBGA-129) — Figure 17. Power supply scheme (UFBGA129 and WLCSP100 packages)
Figure 17. Power supply scheme (UFBGA129 and WLCSP100 packages)
P170 · p170_fig01EXACT PACKAGE
STM32WB55VEQ7 (UFBGA-129) — Figure 38. UFBGA129 package outline
Figure 38. UFBGA129 package outline
P171 · p171_fig01EXACT PACKAGE
STM32WB55VEQ7 (UFBGA-129) — Figure 39. UFBGA129 recommended footprint
Figure 39. UFBGA129 recommended footprint
P172 · p172_fig01EXACT PACKAGE
STM32WB55VEQ7 (UFBGA-129) — Figure 40. UFBGA129 marking example (package top view)
Figure 40. UFBGA129 marking example (package top view)
P1 · p01_fig01881×755px
STM32WB55VEQ7 (UFBGA-129) — STM32WB55xx STM32WB35xx Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4
STM32WB55xx STM32WB35xx Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4
P58 · p58_fig011546×951px
STM32WB55VEQ7 (UFBGA-129) — Figure 10. STM32WB55Cx and STM32WB35Cx UFQFPN48 pinout(1)(2)
Figure 10. STM32WB55Cx and STM32WB35Cx UFQFPN48 pinout(1)(2)
P58 · p58_fig021546×1135px
STM32WB55VEQ7 (UFBGA-129) — Figure 11. STM32WB55Rx VFQFPN68 pinout(1)(2)
Figure 11. STM32WB55Rx VFQFPN68 pinout(1)(2)
P82 · p82_fig01P82
STM32WB55VEQ7 (UFBGA-129) — Datasheet Page 82 (p82_fig01)
Datasheet Page 82 (p82_fig01)
P152 · p152_fig011546×702px
STM32WB55VEQ7 (UFBGA-129) — Figure 30. Typical connection diagram using the ADC
Figure 30. Typical connection diagram using the ADC
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (STM32WB55VEQ7)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32WB55VEQ7 (UFBGA-129) is a 129-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.58 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, UART, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
70 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.58 mm (A1=0.20 mm)
Package family: BGA (UFBGA-129)
Pin Count & Lead PitchN / e
129 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, UART, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3 BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol129 auto-grouped pins
OK
IPC-7351B Land Pattern129 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-129)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.58mm · e=0.50mm
Pad Size (W × L)Level B
0.23 × 0.23 mm
Pins / Total PadsTopology
129P / 129Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-129
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32WB55VEQ7 (UFBGA-129)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32WB55VEQ7 (UFBGA-129)?

Manufactured by ST, the STM32WB55VEQ7 is housed in a UFBGA-129 package with 129 pins and a 0.50 mm lead pitch. Key pins include: A1 (PE1: Multiplexed I/O & Peripheral Pin PE1 (General)), A2 (PB6: Multiplexed I/O & Peripheral Pin PB6 (UART)), A3 (PB5: Multiplexed I/O & Peripheral Pin PB5 (SPI)), A6 (PD5: Multiplexed I/O & Peripheral Pin PD5 (General)), A7 (PD10: Multiplexed I/O & Peripheral Pin PD10 (General)), A8 (VDD_DCAP4: Power Supply Input (VDD_DCAP4 — 3.3V VDD (Max 4.0V))).

What are the IPC-7351B PCB Footprint dimensions for STM32WB55VEQ7?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WB55VEQ7 (UFBGA-129) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 129 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WB55VEQ7?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WB55VEQ7 (ST, UFBGA-129) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (129 pins) & STM32WB55 / STM32WB35 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
A2PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART.
A3PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSIUSART1CK. Supported peripheral buses: SPI.
A6PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
A7PD10Digital_IOSignal terminal PD10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General.
A8VDD_DCAP4Power_InPrimary positive power supply input (VDD_DCAP4) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A11PA13 (JTMS SWDIO)_Digital_IOSignal terminal PA13 (JTMS SWDIO)_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMS SWDIO)_. Supported peripheral buses: USB, SWD/JTAG.
A12VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A13PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART.
B1PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
B2PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
B3PB4 (NJTRST)Digital_IOSignal terminal PB4 (NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA, SPI1_MISOUSART1CTS. Supported peripheral buses: SPI, I2C, SWD/JTAG.
B4PD12Digital_IOSignal terminal PD12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General.
B5PD11Digital_IOSignal terminal PD11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD11. Supported peripheral buses: General.
B6PD8Digital_IOSignal terminal PD8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD8. Supported peripheral buses: General.
B7PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
B8VSS_DCAP4GND0V electrical ground return terminal (VSS_DCAP4) for internal core logic, I/O drivers, and analog sub-blocks.
B9PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
B10PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: RTC/CLK.
B11PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSCM4EVENTOUT. Supported peripheral buses: SPI.
B12VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B13PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOUSART1CTS. Supported peripheral buses: USB, SPI, PWM.
C1PD13Digital_IOSignal terminal PD13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General.
C2PD15Digital_IOSignal terminal PD15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: PWM.
C3PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: I2C.
C4PB3 (JTDO)Digital_IOSignal terminal PB3 (JTDO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB3 (JTDO). Supported peripheral buses: UART, PWM, SWD/JTAG.
C5PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
C6PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI_TSCG5IO1. Supported peripheral buses: SPI.
C7PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKCM4EVENTOUT. Supported peripheral buses: SPI.
C8PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
C9PA15 (JTDI)Digital_IOSignal terminal PA15 (JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS_TSCG3IO1. Supported peripheral buses: SPI, SWD/JTAG.
C10PA14 (JTCK SWCLK)_Digital_IOSignal terminal PA14 (JTCK SWCLK)_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (JTCK SWCLK)_. Supported peripheral buses: I2C, SWD/JTAG.
C11VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C12PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: USB, I2C.
C13PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: USB, SPI.
D2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D3PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: PWM.
D4PD9Digital_IOSignal terminal PD9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD9. Supported peripheral buses: General.
D6PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: I2C.
D8PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKSPI2MISO. Supported peripheral buses: SPI.
D10PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
D11PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
D12PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
E2PC15 - OSC32_OUTDigital_IOSignal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK.
E3PC14 - OSC32_INDigital_IOSignal terminal PC14 - OSC32_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN. Supported peripheral buses: RTC/CLK.
E5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E9VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E11PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO_TSCG1IO3. Supported peripheral buses: SPI, PWM.
E12PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKLPUART1CTS. Supported peripheral buses: SPI, PWM.
F1PH0Digital_IOSignal terminal PH0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0. Supported peripheral buses: General.
F2VDD_DCAP1Power_InPrimary positive power supply input (VDD_DCAP1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F3VSS_DCAP1GND0V electrical ground return terminal (VSS_DCAP1) for internal core logic, I/O drivers, and analog sub-blocks.
F4PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
F6VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F8VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F10PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI_TSCG1IO4. Supported peripheral buses: SPI, RTC/CLK.
F11VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
F12VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F13VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
G1PH3 BOOT0 -Digital_IOSignal terminal PH3 BOOT0 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH3 BOOT0 -. Supported peripheral buses: General.
G2PH1Digital_IOSignal terminal PH1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1. Supported peripheral buses: General.
G3PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: PWM.
G5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
ExplorePartsPackagesMFRsUpload