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STM32G0B1CCU6 (UFQFPN-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32G0B1CCU6

STID: C2829191UFQFPN-48(7x7) · 49 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32G0B1CCU6 (UFQFPN-48(7x7))1PC132PC14-OSC32_I3PC15-OSC32_O4VBAT5VREF+6VDD/VDDA7VSS/VSSA8PF0-OSC_IN9PF1-OSC_OUT10PF2-NRST11PA012PA113PA214PA315PA416PA517PA618PA719PB020PB121PB222PB1023PB1124PB1225PB1349EP48PB947PB846PB745PB644PB543PB442PB341PD340PD239PD138PD037PA1536PA14-BOOT035PA1334PA12[PA10]33PA11[PA9]32PA1031PC730PC629PA928PA827PB1526PB14Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849E=7.00mm · Pitch e=0.50mmD=7.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
2PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
3PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
4VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
5VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
6VDD/VDDAPowerPower Supply Input (VDD/VDDA — 3.3V VDD (Max 4.0V))
7VSS/VSSAGNDGround Reference Pin (VSS/VSSA)
8PF0-OSC_INI/OMultiplexed I/O & Peripheral Pin PF0-OSC_IN (RTC/CLK)
9PF1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PF1-OSC_OUT (RTC/CLK)
10PF2-NRSTI/OMultiplexed I/O & Peripheral Pin PF2-NRST (General)
11PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
12PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
13PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
14PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
15PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
16PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
17PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
18PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
19PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
20PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
21PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
22PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
23PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
24PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
25PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
26PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
27PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
28PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
29PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
30PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
31PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
32PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
33PA11[PA9]I/OMultiplexed I/O & Peripheral Pin PA11[PA9] (General)
34PA12[PA10]I/OMultiplexed I/O & Peripheral Pin PA12[PA10] (General)
35PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
36PA14-BOOT0I/OMultiplexed I/O & Peripheral Pin PA14-BOOT0 (General)
37PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
38PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
39PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
40PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
41PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
42PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
43PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
44PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
45PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
46PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
47PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
48PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
49EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 PC13
I/O
Multiplexed I/O & Peripheral Pin PC13 (General)
Design note: Signal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32G0B1CCU6 (ST · UFQFPN-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32G0B1CCU6 (UFQFPN-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32G0B1CCU6 (UFQFPN-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32G0B1CCU6 (UFQFPN-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32G0B1CCU6 (UFQFPN-48(7x7)) - 4. Package Dimensions (D×E×A)
UFQFPN-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32G0B1CCU6 (UFQFPN-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32G0B1CCU6 (UFQFPN-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for STM32G0B1CCU
P131 · p131_fig01EXACT PACKAGE
STM32G0B1CCU6 (UFQFPN-48(7x7)) — STM32G0B1xB/C/xE Package information - 6.3 UFQFPN48 package information - UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package
STM32G0B1xB/C/xE Package information - 6.3 UFQFPN48 package information - UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package
P134 · p134_fig01EXACT PACKAGE
STM32G0B1CCU6 (UFQFPN-48(7x7)) — Package information ‘STM32G0B1xB/C/xE - 6.4 LQFP48 package information - LOFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.
Package information ‘STM32G0B1xB/C/xE - 6.4 LQFP48 package information - LOFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.
P1 · p01_fig011755×2398px
STM32G0B1CCU6 (UFQFPN-48(7x7)) — ‘S72 STM32G0B1xB/C/xE - Arm® Cortex®-M0+ 32-bit MCU, up to 512KB Flash, 144KB RAM, - 6x USART, timers, ADC, DAC, comm. I/Fs, 1.7-3.6V
‘S72 STM32G0B1xB/C/xE - Arm® Cortex®-M0+ 32-bit MCU, up to 512KB Flash, 144KB RAM, - 6x USART, timers, ADC, DAC, comm. I/Fs, 1.7-3.6V
P1 · p01_fig02196×196px
STM32G0B1CCU6 (UFQFPN-48(7x7)) — = UFBGA64
= UFBGA64
P1 · p01_fig02P1
STM32G0B1CCU6 (UFQFPN-48(7x7)) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P2 · p02_fig011546×1964px
STM32G0B1CCU6 (UFQFPN-48(7x7)) — PDF Figure p02_fig01 (Page 2 — OTHER_DIAGRAM)
PDF Figure p02_fig01 (Page 2 — OTHER_DIAGRAM)
P4 · p04_fig011546×2318px
STM32G0B1CCU6 (UFQFPN-48(7x7)) — Contents ‘STM32G0B1xB/C/xE - 5.3.4 Embedded voltage reference ......... cece cece eee eeeeeeeee es TO - 5.3.5 Supply current characteristics ......... 00.0. 0eeeeeeeeeeeee ee TA
Contents ‘STM32G0B1xB/C/xE - 5.3.4 Embedded voltage reference ......... cece cece eee eeeeeeeee es TO - 5.3.5 Supply current characteristics ......... 00.0. 0eeeeeeeeeeeee ee TA
P106 · p106_fig011755×2003px
STM32G0B1CCU6 (UFQFPN-48(7x7)) — Electrical characteristics STM32G0B1xB/C/xE - Figure 28. ADC accuracy characteristics - Code -_-
Electrical characteristics STM32G0B1xB/C/xE - Figure 28. ADC accuracy characteristics - Code -_-
P113 · p113_fig011761×2599px
STM32G0B1CCU6 (UFQFPN-48(7x7)) — STM32G0B1xB/C/xE Electrical characteristics - Table 67. COMP characteristics") (continued) - Spit [Prete | anons [i [tr]
STM32G0B1xB/C/xE Electrical characteristics - Table 67. COMP characteristics") (continued) - Spit [Prete | anons [i [tr]
P144 · p144_fig01All Packages in PDF
STM32G0B1CCU6 (UFQFPN-48(7x7)) — Package information STM32G0B1xB/C/xE - Table 90. LQFP64 package mechanical data (continued) - ee ee ee
Package information STM32G0B1xB/C/xE - Table 90. LQFP64 package mechanical data (continued) - ee ee ee

Technical Specifications & Part Details (STM32G0B1CCU6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32G0B1CCU6 (UFQFPN-48(7x7)) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.60 mm (A1=0.03 mm)
Package family: QFN (UFQFPN-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PA14-BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 5.50×5.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFQFPN-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.60mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.85 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFQFPN-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32G0B1CCU6 (UFQFPN-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32G0B1CCU6 (UFQFPN-48(7x7))?

Manufactured by ST, the STM32G0B1CCU6 is housed in a UFQFPN-48(7x7) package with 49 pins and a 0.50 mm lead pitch. Key pins include: 1 (PC13: Multiplexed I/O & Peripheral Pin PC13 (General)), 2 (PC14-OSC32_IN: Multiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)), 3 (PC15-OSC32_OUT: Multiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)), 4 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 5 (VREF+: Multiplexed I/O & Peripheral Pin VREF+ (General)), 6 (VDD/VDDA: Power Supply Input (VDD/VDDA — 3.3V VDD (Max 4.0V))).

What are the IPC-7351B PCB Footprint dimensions for STM32G0B1CCU6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32G0B1CCU6 (UFQFPN-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.50 × 5.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32G0B1CCU6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32G0B1CCU6 (ST, UFQFPN-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & STM32G0B1CCU Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
2PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
3PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
4VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
5VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
6VDD/VDDAPower_InPrimary positive power supply input (VDD/VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
7VSS/VSSAGND0V electrical ground return terminal (VSS/VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
8PF0-OSC_INDigital_IOSignal terminal PF0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF0-OSC_IN. Supported peripheral buses: RTC/CLK.
9PF1-OSC_OUTDigital_IOSignal terminal PF1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1-OSC_OUT. Supported peripheral buses: RTC/CLK.
10PF2-NRSTDigital_IOSignal terminal PF2-NRST (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2-NRST. Supported peripheral buses: General.
11PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
12PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
13PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
14PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
15PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
16PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
17PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
18PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
19PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
20PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
21PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
22PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
23PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
24PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
25PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
26PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
27PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
28PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
29PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
30PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
31PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
32PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
33PA11[PA9]Digital_IOSignal terminal PA11[PA9] (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11[PA9]. Supported peripheral buses: General.
34PA12[PA10]Digital_IOSignal terminal PA12[PA10] (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12[PA10]. Supported peripheral buses: General.
35PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
36PA14-BOOT0Digital_IOSignal terminal PA14-BOOT0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14-BOOT0. Supported peripheral buses: General.
37PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
38PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
39PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
40PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
41PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
42PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
43PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
44PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
45PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
46PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
47PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
48PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
49EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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