TO-92-2.54mm · 3P
3P4.8×3.7×4.80mmP=2.54mm
KP1051 (TO-92-2.54mm)
Synchronized Pinout (Symbol / 2D / 3D) (4/4)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | DRAIN | Analog | Multiplexed I/O & Peripheral Pin DRAIN (General) |
| 2 | CS | I/O | Multiplexed I/O & Peripheral Pin CS (General) |
| 3 | VDD | Power | Power Supply Input (VDD — 3.3V / 5.0V Standard Logic) |
| 4 | TAB | I/O | Multiplexed I/O & Peripheral Pin TAB (General) |
PIN 1 DRAIN
AnalogMultiplexed I/O & Peripheral Pin DRAIN (General)
Design note: Signal terminal DRAIN (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DRAIN. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (4 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SOT-223-4 · 6.50×3.50mm · Pitch 2.30mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (4 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for KP1051
P1 · p01_fig01EXACT PACKAGE
P2 · p02_fig01EXACT PACKAGE
P2 · p02_fig02EXACT PACKAGE
P2 · p02_fig03EXACT PACKAGE
P2 · p02_fig04EXACT PACKAGE
P2 · p02_fig05EXACT PACKAGE
P3 · p03_fig01EXACT PACKAGE
P10 · p10_fig01EXACT PACKAGE
P1 · p01_fig01P1
P2 · p02_fig04P2
P8 · p08_fig011840×2290px
P10 · p10_fig01P10
Page 1 / 2 (13 extracted figures)
Technical Specifications & Part Details (KP1051FPA)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:KP1051FPA (SOT-223-4) is a 4-pin low-dropout linear voltage regulator (ldo) featuring a 6.50 × 3.50 × 1.60 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.50 × 3.50 × 1.60 mm (A1=0.06 mm)
Package family: SOT223 (SOT-223-4)
Pin Count & Lead PitchN / e
4 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol4 auto-grouped pins
IPC-7351B Land Pattern4 pads · Pitch 2.30mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — KP1051 (4)
SOT-223-4 · 4P
SOP-8 · 8P
SOP-8 · 8P
Mechanical Dimensions & Land Pattern (SOT-223-4)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
6.50 × 3.50 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=2.30mm
Pad Size (W × L)Level B
0.95 × 2.00 mm
Pins / Total PadsTopology
4P / 4Pad (SOT_TAB)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SOT-223-4 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — KP1051FPA (SOT-223-4)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of KP1051FPA (SOT-223-4)?
Manufactured by Kiwi Instruments, the KP1051FPA is housed in a SOT-223-4 package with 4 pins and a 2.30 mm lead pitch. Key pins include: 1 (DRAIN: Multiplexed I/O & Peripheral Pin DRAIN (General)), 2 (CS: Multiplexed I/O & Peripheral Pin CS (General)), 3 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 4 (TAB: Multiplexed I/O & Peripheral Pin TAB (General)).
What are the IPC-7351B PCB Footprint dimensions for KP1051FPA?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), KP1051FPA (SOT-223-4) has a nominal body envelope of 3.50 × 6.50 mm, pitch e = 2.30 mm, and 4 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for KP1051FPA?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for KP1051FPA (Kiwi Instruments, SOT-223-4) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (4 pins) & KP1051 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | DRAIN | Analog | Signal terminal DRAIN (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DRAIN. Supported peripheral buses: General. |
| 2 | CS | Digital_IO | Signal terminal CS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS. Supported peripheral buses: General. |
| 3 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 4 | TAB | Digital_IO | Signal terminal TAB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TAB. Supported peripheral buses: General. |