Mechanical Dimensions & Land Pattern (LQFP-44-(20x20))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
20.00 × 20.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 2.00 mm
Pins / Total PadsTopology
144P / 144Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-44-(20x20) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32H523ZCT6 (LQFP-44-(20x20))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32H523ZCT6 (LQFP-44-(20x20))?
Manufactured by ST, the STM32H523ZCT6 is housed in a LQFP-44-(20x20) package with 144 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), 2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), 3 (PE4: Multiplexed I/O & Peripheral Pin PE4 (General)), 4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (General)), 5 (PH0OSC IN -_ (PH0): Multiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (RTC/CLK)), 6 (PH1OSC OUT -_ (PH1): Multiplexed I/O & Peripheral Pin PH1OSC OUT -_ (PH1) (RTC/CLK)).
What are the IPC-7351B PCB Footprint dimensions for STM32H523ZCT6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H523ZCT6 (LQFP-44-(20x20)) has a nominal body envelope of 20.00 × 20.00 mm, pitch e = 0.50 mm, and 144 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H523ZCT6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H523ZCT6 (ST, LQFP-44-(20x20)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (144 pins) & STM32H523 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PE2 | Digital_IO | Signal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General. |
| 2 | PE3 | Digital_IO | Signal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General. |
| 3 | PE4 | Digital_IO | Signal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General. |
| 4 | PE5 | Digital_IO | Signal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General. |
| 5 | PH0OSC IN -_ (PH0) | Digital_IO | Signal terminal PH0OSC IN -_ (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0OSC IN -_ (PH0). Supported peripheral buses: RTC/CLK. |
| 6 | PH1OSC OUT -_ (PH1) | Digital_IO | Signal terminal PH1OSC OUT -_ (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1OSC OUT -_ (PH1). Supported peripheral buses: RTC/CLK. |
| 7 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 8 | VSSA | GND | 0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| 9 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 10 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_SCKSPI3RDY. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 11 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM. |
| 12 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: ADC, PWM. |
| 13 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, SPI3_MOSI. Supported peripheral buses: SPI, ADC, PWM. |
| 14 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_MOSI, SPI1_NSS, SPI3_NSS. Supported peripheral buses: SPI, ADC. |
| 15 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC, PWM. |
| 16 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC, PWM. |
| 17 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM. |
| 18 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 19 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK, SPI2_NSS. Supported peripheral buses: SPI, ADC, PWM. |
| 20 | PF8 | Digital_IO | Signal terminal PF8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF8. Supported peripheral buses: General. |
| 21 | PB10 | Digital_IO | Signal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL, SPI2_SCK. Supported peripheral buses: UART, SPI, I2C, PWM. |
| 22 | VCAP | Digital_IO | Signal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General. |
| 23 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 24 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 25 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI. |
| 26 | PC0 | Digital_IO | Signal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General. |
| 27 | PC1 | Digital_IO | Signal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General. |
| 28 | PC2 | Digital_IO | Signal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General. |
| 29 | PC3 | Digital_IO | Signal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General. |
| 30 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 31 | VSSA | GND | 0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| 32 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: USB, UART, SPI, PWM. |
| 33 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: USB, UART, SPI. |
| 34 | PA13(JTMS/SW DIO) | Digital_IO | Signal terminal PA13(JTMS/SW DIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13(JTMS/SW DIO). Supported peripheral buses: SWD/JTAG. |
| 35 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 36 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 37 | PA14(JTCK/ SWCLK) | Digital_IO | Signal terminal PA14(JTCK/ SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14(JTCK/ SWCLK). Supported peripheral buses: SWD/JTAG. |
| 38 | PA15 (JTDI) | Digital_IO | Signal terminal PA15 (JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, SWD/JTAG. |
| 39 | PB3(JTDO/ TRACESWO) | Digital_IO | Signal terminal PB3(JTDO/ TRACESWO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK, SPI3_SCK. Supported peripheral buses: SPI, I2C, SWD/JTAG. |
| 40 | PB4 (NJTRST) | Digital_IO | Signal terminal PB4 (NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, SPI3_MISO, SPI2_NSS. Supported peripheral buses: SPI, I2C, SWD/JTAG. |
| 41 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSI, SPI3_MOSI. Supported peripheral buses: UART, SPI, I2C, PWM. |
| 42 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART, I2C. |
| 43 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MISO. Supported peripheral buses: UART, SPI, I2C. |
| 44 | BOOT0 | Digital_IO | Signal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General. |
| 45 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_RDY, SPI3_NSS. Supported peripheral buses: SPI, I2C. |
| 46 | VCAP | Digital_IO | Signal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General. |
| 47 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 48 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 49 | PF11 | Digital_IO | Signal terminal PF11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF11. Supported peripheral buses: General. |
| 50 | PF12 | Digital_IO | Signal terminal PF12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF12. Supported peripheral buses: General. |
| 51 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 52 | PB13 | Digital_IO | Signal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SMBA, SPI2_SCK. Supported peripheral buses: UART, SPI, I2C, PWM. |
| 53 | PB14 | Digital_IO | Signal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI. |
| 54 | PB15 | Digital_IO | Signal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI, SPI1_MOSI. Supported peripheral buses: UART, SPI, PWM, RTC/CLK. |
| 55 | PD8 | Digital_IO | Signal terminal PD8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD8. Supported peripheral buses: UART. |
| 56 | PD9 | Digital_IO | Signal terminal PD9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD9. Supported peripheral buses: UART. |
| 57 | PD10 | Digital_IO | Signal terminal PD10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General. |
| 58 | PD11 | Digital_IO | Signal terminal PD11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD11. Supported peripheral buses: UART, SPI. |
| 59 | PD12 | Digital_IO | Signal terminal PD12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: UART, I2C, PWM. |
| 60 | PD13 | Digital_IO | Signal terminal PD13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: I2C, PWM. |
| 61 | PD14 | Digital_IO | Signal terminal PD14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General. |
| 62 | PD15 | Digital_IO | Signal terminal PD15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General. |
| 63 | PC6 | Digital_IO | Signal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: UART, PWM. |
| 64 | PE11 | Digital_IO | Signal terminal PE11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE11. Supported peripheral buses: General. |