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STM32U031F8P6 (TSSOP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32U031F8P6

STID: C22808553TSSOP-20 · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32U031F8P6 (TSSOP-20)1PB92VSS3VDD4PC14-OSC32IN5PC15-OSC32OU6PF2-NRST7VDDA/VREF+8PA0-CKIN9PA210PA420PF3-BOOT0 (B19PB718PB617PA13(SWDIO)16PA12[PA10]15PA11[PA9]14PA1013PB112PB011PA6Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=4.40mm · Pitch e=0.65mmD=6.50mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.40mm × 6.50mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI, I2C)
2VSSGNDGround Reference Pin (VSS)
3VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
4PC14-OSC32INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32IN (RTC/CLK)
5PC15-OSC32OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32OUT (RTC/CLK)
6PF2-NRSTI/OMultiplexed I/O & Peripheral Pin PF2-NRST (RTC/CLK)
7VDDA/VREF+PowerPower Supply Input (VDDA/VREF+ — 3.3V VDD (Max 4.0V))
8PA0-CKINI/OMultiplexed I/O & Peripheral Pin PA0-CKIN (UART, ADC)
9PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC)
10PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
11PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, I2C, ADC)
12PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC)
13PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART)
14PA10I/OMultiplexed I/O & Peripheral Pin PA10 (I2C, RTC/CLK)
15PA11[PA9]I/OMultiplexed I/O & Peripheral Pin PA11[PA9] (UART, SPI)
16PA12[PA10]I/OMultiplexed I/O & Peripheral Pin PA12[PA10] (SPI)
17PA13(SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13(SWDIO) (SWD/JTAG)
18PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C)
19PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
20PF3-BOOT0 (BOOT0)I/OMultiplexed I/O & Peripheral Pin PF3-BOOT0 (BOOT0) (General)
PIN 1 PB9
I/O
Multiplexed I/O & Peripheral Pin PB9 (SPI, I2C)
Design note: Alt: IR OUTI2C2 SDA I2C1 SDA_SPI2NSSUSART, 3_RXLPT, I_M1CH4 E, V_ENTOUT,_ ,_ ,
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32U031F8P6 (ST · TSSOP-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32U031F8P6 (TSSOP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32U031F8P6 (TSSOP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32U031F8P6 (TSSOP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32U031F8P6 (TSSOP-20) - 4. Package Dimensions (D×E×A)
TSSOP-20 · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32U031F8P6 (TSSOP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32U031F8P6 (TSSOP-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for STM32U031
P26 · p26_fig01EXACT PACKAGE
STM32U031F8P6 (TSSOP-20) — Figure 3. TSSOP20 pinout
Figure 3. TSSOP20 pinout
P103 · p103_fig01EXACT PACKAGE
STM32U031F8P6 (TSSOP-20) — Figure 32. TSSOP20 - Outline D
Figure 32. TSSOP20 - Outline D
P104 · p104_fig01EXACT PACKAGE
STM32U031F8P6 (TSSOP-20) — Figure 33. TSSOP20 - Footprint example
Figure 33. TSSOP20 - Footprint example
P1 · p01_fig011408×522px
STM32U031F8P6 (TSSOP-20) — • 430 ULPMark™-CP
• 430 ULPMark™-CP
P26 · p26_fig021533×708px
STM32U031F8P6 (TSSOP-20) — Figure 4. WLCSP27 ballout
Figure 4. WLCSP27 ballout
P26 · p26_fig01P26
STM32U031F8P6 (TSSOP-20) — Datasheet Page 26 (p26_fig01)
Datasheet Page 26 (p26_fig01)
P40 · p40_fig011436×1189px
STM32U031F8P6 (TSSOP-20) — Figure 12. Power supply scheme
Figure 12. Power supply scheme
P40 · p40_fig01P40
STM32U031F8P6 (TSSOP-20) — Datasheet Page 40 (p40_fig01)
Datasheet Page 40 (p40_fig01)
P87 · p87_fig01908×757px
STM32U031F8P6 (TSSOP-20) — Figure 24. ADC accuracy characteristics
Figure 24. ADC accuracy characteristics
P87 · p87_fig021603×614px
STM32U031F8P6 (TSSOP-20) — Figure 25. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch
Figure 25. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch
P87 · p87_fig01P87
STM32U031F8P6 (TSSOP-20) — Datasheet Page 87 (p87_fig01)
Datasheet Page 87 (p87_fig01)
P103 · p103_fig01P103
STM32U031F8P6 (TSSOP-20) — Datasheet Page 103 (p103_fig01)
Datasheet Page 103 (p103_fig01)
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (STM32U031F8P6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32U031F8P6 (TSSOP-20) is a 20-pin embedded microcontroller unit (mcu) featuring a 6.50 × 4.40 × 1.20 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
56 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
15 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.20 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PF3-BOOT0 (BOOT0)): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TSSOP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32U031F8P6 (TSSOP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32U031F8P6 (TSSOP-20)?

Manufactured by ST, the STM32U031F8P6 is housed in a TSSOP-20 package with 20 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: 1 (PB9: Multiplexed I/O & Peripheral Pin PB9 (SPI, I2C)), 2 (VSS: Ground Reference Pin (VSS)), 3 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), 4 (PC14-OSC32IN: Multiplexed I/O & Peripheral Pin PC14-OSC32IN (RTC/CLK)), 5 (PC15-OSC32OUT: Multiplexed I/O & Peripheral Pin PC15-OSC32OUT (RTC/CLK)), 6 (PF2-NRST: Multiplexed I/O & Peripheral Pin PF2-NRST (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32U031F8P6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32U031F8P6 (TSSOP-20) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32U031F8P6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32U031F8P6 (ST, TSSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & STM32U031 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: SPI, I2C.
2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
3VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
4PC14-OSC32INDigital_IOSignal terminal PC14-OSC32IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14-OSC32IN. Supported peripheral buses: RTC/CLK.
5PC15-OSC32OUTDigital_IOSignal terminal PC15-OSC32OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15-OSC32OUT. Supported peripheral buses: RTC/CLK.
6PF2-NRSTDigital_IOSignal terminal PF2-NRST (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2-NRST. Supported peripheral buses: RTC/CLK.
7VDDA/VREF+Power_InPrimary positive power supply input (VDDA/VREF+) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
8PA0-CKINDigital_IOSignal terminal PA0-CKIN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0-CKIN. Supported peripheral buses: UART, ADC.
9PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC.
10PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC.
11PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: UART, I2C, ADC.
12PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: UART, SPI, ADC.
13PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART.
14PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: I2C, RTC/CLK.
15PA11[PA9]Digital_IOSignal terminal PA11[PA9] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOSPI2MISO. Supported peripheral buses: UART, SPI.
16PA12[PA10]Digital_IOSignal terminal PA12[PA10] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI_SPI2MOSIUSART1. Supported peripheral buses: SPI.
17PA13(SWDIO)Digital_IOSignal terminal PA13(SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13(SWDIO). Supported peripheral buses: SWD/JTAG.
18PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
19PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
20PF3-BOOT0 (BOOT0)Digital_IOSignal terminal PF3-BOOT0 (BOOT0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF3-BOOT0 (BOOT0). Supported peripheral buses: General.
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