Mechanical Dimensions & Land Pattern (LQFP-144(20x20))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
20.00 × 20.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.35 × 1.35 mm
Pins / Total PadsTopology
144P / 144Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-144(20x20) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32H7R3Z8T6 (LQFP-144(20x20))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32H7R3Z8T6 (LQFP-144(20x20))?
Manufactured by ST, the STM32H7R3Z8T6 is housed in a LQFP-144(20x20) package with 144 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: 1 (PB8: Multiplexed I/O & Peripheral Pin PB8 (General)), 2 (PB9: Multiplexed I/O & Peripheral Pin PB9 (General)), 3 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 4 (PC13: Multiplexed I/O & Peripheral Pin PC13 (General)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).
What are the IPC-7351B PCB Footprint dimensions for STM32H7R3Z8T6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H7R3Z8T6 (LQFP-144(20x20)) has a nominal body envelope of 20.00 × 20.00 mm, pitch e = 0.50 mm, and 144 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H7R3Z8T6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H7R3Z8T6 (ST, LQFP-144(20x20)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (144 pins) & STM32H7R3L8H / STM32H7R3V8H / STM32H7R3Z8T Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General. |
| 2 | PB9 | Digital_IO | Signal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General. |
| 3 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 4 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General. |
| 5 | IO2 | Digital_IO | GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1 |
| 6 | IO3 | Digital_IO | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 8 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 9 | PE3 | Digital_IO | Signal terminal PE3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General. |
| 10 | PE4 | Digital_IO | Signal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSS_SAI1FSA. Supported peripheral buses: SPI. |
| 11 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 12 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 13 | PH0 - OSC IN(PH_ 0) | Digital_IO | Signal terminal PH0 - OSC IN(PH_ 0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC IN(PH_ 0). Supported peripheral buses: RTC/CLK. |
| 14 | PH1 - OSC OUT(_ PH1) | Digital_IO | Signal terminal PH1 - OSC OUT(_ PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC OUT(_ PH1). Supported peripheral buses: RTC/CLK. |
| 15 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 16 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 17 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 18 | PC0 | Digital_IO | Signal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC. |
| 19 | PC1 | Digital_IO | Signal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC. |
| 20 | PC2 | Digital_IO | Signal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, ADC, PWM. |
| 21 | PC3 | Digital_IO | Signal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC, PWM. |
| 22 | VSSA | GND | 0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| 23 | VREFM | Analog | Signal terminal VREFM (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREFM. Supported peripheral buses: General. |
| 24 | VREFP | Analog | Signal terminal VREFP (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREFP. Supported peripheral buses: General. |
| 25 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 26 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI6_NSS. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 27 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM. |
| 28 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM. |
| 29 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI5_RDYSPI1RDY. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 30 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 31 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 32 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS, SPI6_NSS. Supported peripheral buses: UART, SPI, ADC. |
| 33 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK, SPI6_SCK. Supported peripheral buses: SPI, ADC. |
| 34 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, SPI6_MISO. Supported peripheral buses: SPI, ADC, PWM. |
| 35 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, SPI6_MOSI. Supported peripheral buses: SPI, ADC, PWM. |
| 36 | PC4 | Digital_IO | Signal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: UART, ADC. |
| 37 | PC5 | Digital_IO | Signal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: UART, ADC. |
| 38 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 39 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM. |
| 40 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: SPI, RTC/CLK. |
| 41 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 42 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 43 | VCAP1 | Digital_IO | Signal terminal VCAP1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP1. Supported peripheral buses: General. |
| 44 | PO1 | Digital_IO | Signal terminal PO1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PO1. Supported peripheral buses: General. |
| 45 | VDDXSPI1 | Power_In | Primary positive power supply input (VDDXSPI1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 46 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 47 | PP4 | Digital_IO | Signal terminal PP4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP4. Supported peripheral buses: General. |
| 48 | PP2 | Digital_IO | Signal terminal PP2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP2. Supported peripheral buses: General. |
| 49 | PP3 | Digital_IO | Signal terminal PP3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP3. Supported peripheral buses: General. |
| 50 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 51 | VDDXSPI1 | Power_In | Primary positive power supply input (VDDXSPI1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 52 | PO5 | Digital_IO | Signal terminal PO5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PO5. Supported peripheral buses: General. |
| 53 | PO4 | Digital_IO | Signal terminal PO4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PO4. Supported peripheral buses: General. |
| 54 | PP5 | Digital_IO | Signal terminal PP5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP5. Supported peripheral buses: General. |
| 55 | PP0 | Digital_IO | Signal terminal PP0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP0. Supported peripheral buses: General. |
| 56 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 57 | VDDXSPI1 | Power_In | Primary positive power supply input (VDDXSPI1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 58 | PP6 | Digital_IO | Signal terminal PP6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP6. Supported peripheral buses: General. |
| 59 | PO2 | Digital_IO | Signal terminal PO2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PO2. Supported peripheral buses: General. |
| 60 | PP7 | Digital_IO | Signal terminal PP7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP7. Supported peripheral buses: General. |
| 61 | PP1 | Digital_IO | Signal terminal PP1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP1. Supported peripheral buses: General. |
| 62 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 63 | VDDXSPI1 | Power_In | Primary positive power supply input (VDDXSPI1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 64 | PO0 | Digital_IO | Signal terminal PO0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PO0. Supported peripheral buses: General. |