PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC24HJ128GP502-I/MM (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC24HJ128GP502-I/MM is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (AN4/C1IN-/RP2/CN6/RB2: Multiplexed I/O & Peripheral Pin AN4/C1IN-/RP2/CN6/RB2 (General)), 4 (AN5/C1IN+/RP3/CN7/RB3: Multiplexed I/O & Peripheral Pin AN5/C1IN+/RP3/CN7/RB3 (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (OSC1/CLKI/CN30/RA2: Multiplexed I/O & Peripheral Pin OSC1/CLKI/CN30/RA2 (RTC/CLK)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC24HJ128GP502-I/MM?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC24HJ128GP502-I/MM?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC24HJ128GP502-I/MM (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 6.00mm × 6.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	IO1	I/O	General Purpose Digital I/O Pin IO1
2	IO2	I/O	General Purpose Digital I/O Pin IO2
3	AN4/C1IN-/RP2/CN6/RB2	I/O	Multiplexed I/O & Peripheral Pin AN4/C1IN-/RP2/CN6/RB2 (General)
4	AN5/C1IN+/RP3/CN7/RB3	I/O	Multiplexed I/O & Peripheral Pin AN5/C1IN+/RP3/CN7/RB3 (General)
5	VSS	GND	Ground Reference Pin (VSS)
6	OSC1/CLKI/CN30/RA2	I/O	Multiplexed I/O & Peripheral Pin OSC1/CLKI/CN30/RA2 (RTC/CLK)
7	NC	NC	No Connect (Leave Floating)
8	SOSCI/RP4/CN1/PMBE/RB4	I/O	Multiplexed I/O & Peripheral Pin SOSCI/RP4/CN1/PMBE/RB4 (General)
9	IO4	I/O	GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10	VDD	Power	Power Supply Input (VDD — 3.0V to 3.6V)
11	IO6	I/O	GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12	IO7	I/O	GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13	INT0/RP7/CN23/PMD5/RB7	I/O	Multiplexed I/O & Peripheral Pin INT0/RP7/CN23/PMD5/RB7 (General)
14	IO16	I/O	GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15	IO17	I/O	GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16	VSS	GND	Ground Reference Pin (VSS)
17	VCAP	I/O	Multiplexed I/O & Peripheral Pin VCAP (General)
18	IO19	I/O	GPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19	IO20	I/O	GPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20	IO9	I/O	GPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
21	IO10	I/O	GPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22	IO11	I/O	GPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23	IO12	I/O	GPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24	AVSS	GND	Ground Reference Pin (AVSS)
25	AVDD	Power	Power Supply Input (AVDD — 3.0V to 3.6V)
26	MCLR#	I/O	Multiplexed I/O & Peripheral Pin MCLR# (General)
27	AN0/VREF+/CN2/RA0	Analog	Multiplexed I/O & Peripheral Pin AN0/VREF+/CN2/RA0 (General)
28	AN1/VREF-/CN3/RA1	Analog	Multiplexed I/O & Peripheral Pin AN1/VREF-/CN3/RA1 (General)
29	29	I/O	Multiplexed I/O & Peripheral Pin 29 (General)

PIN 1 IO1

I/O

General Purpose Digital I/O Pin IO1

Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) - 2. Standard Pinout (Top View)

True package pinout (29 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) - 4. Package Dimensions (D×E×A)

QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) - 5. Recommended Land Pattern

IPC-7351B Footprint (29 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)

Showing 1–11 of 11 uncropped original figures for PIC24HJ32GP3 / PIC24HJ128GP

P1 · p01_fig01376×200px

16-bit Microcontrollers (up to 128 KB Flash and 8K SRAM) with Advanced Analog

P53 · p53_fig011625×913px

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

P53 · p53_fig021777×993px

FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS

P54 · p54_fig01867×654px

PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) — Setting the WR bit (NVMCON<15>) starts the opera- tion, and the WR bit is automatically cleared when the operation is finished.

Setting the WR bit (NVMCON<15>) starts the opera- tion, and the WR bit is automatically cleared when the operation is finished.

P54 · p54_fig021783×379px

PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) — EQUATION 5-1: PROGRAMMING TIME | For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN<5:0> bits (see Register 9-4) are set to ‘b111111, the minimum row write time is equal to Equation 5-2. | 5.5.1 KEY

EQUATION 5-1: PROGRAMMING TIME | For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN<5:0> bits (see Register 9-4) are set to ‘b111111, the minimum row write time is equal to Equation 5-2. | 5.5.1 KEY

P277 · p277_fig01867×912px

FIGURE 25-1: CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1,2,3)

P277 · p277_fig01P277

Datasheet Page 277 (p277_fig01)

P364 · p364_fig011777×2354px

PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) — DS70293G-page 364 © 2007-2012 Microchip Technology Inc.

P364 · p364_fig01P364

Datasheet Page 364 (p364_fig01)

P366 · p366_fig011777×2356px

PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) — DS70293G-page 366 © 2007-2012 Microchip Technology Inc.

P368 · p368_fig011777×2361px

PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) — DS70293G-page 368 © 2007-2012 Microchip Technology Inc.

Technical Specifications & Part Details (PIC24HJ128GP502-I/MM)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 0.90 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 3.0V to 3.6V supply operation across -40°C to +125°C with integrated UART, SPI, I2C, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

3.0V to 3.6V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +125°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

7.37 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

6.00 × 6.00 × 0.90 mm (A1=0.03 mm)

Package family: QFN (QFN-28-EP(6x6))

Pin Count & Lead PitchN / e

28 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

UART, SPI, I2C, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol29 auto-grouped pins

IPC-7351B Land Pattern29 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteEPAD 4.70×4.70mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

6.00 × 6.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.90mm · e=0.65mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-28-EP(6x6)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC24HJ128GP502-I/MM (QFN-28-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC24HJ128GP502-I/MM (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC24HJ128GP502-I/MM is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (AN4/C1IN-/RP2/CN6/RB2: Multiplexed I/O & Peripheral Pin AN4/C1IN-/RP2/CN6/RB2 (General)), 4 (AN5/C1IN+/RP3/CN7/RB3: Multiplexed I/O & Peripheral Pin AN5/C1IN+/RP3/CN7/RB3 (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (OSC1/CLKI/CN30/RA2: Multiplexed I/O & Peripheral Pin OSC1/CLKI/CN30/RA2 (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for PIC24HJ128GP502-I/MM?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC24HJ128GP502-I/MM (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC24HJ128GP502-I/MM?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC24HJ128GP502-I/MM (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & PIC24HJ32GP3 / PIC24HJ128GP Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	IO1	Digital_IO	General Purpose Digital I/O Pin IO1
2	IO2	Digital_IO	General Purpose Digital I/O Pin IO2
3	AN4/C1IN-/RP2/CN6/RB2	Digital_IO	Signal terminal AN4/C1IN-/RP2/CN6/RB2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AN4/C1IN-/RP2/CN6/RB2. Supported peripheral buses: General.
4	AN5/C1IN+/RP3/CN7/RB3	Digital_IO	Signal terminal AN5/C1IN+/RP3/CN7/RB3 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AN5/C1IN+/RP3/CN7/RB3. Supported peripheral buses: General.
5	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6	OSC1/CLKI/CN30/RA2	Digital_IO	Signal terminal OSC1/CLKI/CN30/RA2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC1/CLKI/CN30/RA2. Supported peripheral buses: RTC/CLK.
7	NC	No_Connect	No Connect (Leave Floating)
8	SOSCI/RP4/CN1/PMBE/RB4	Digital_IO	Signal terminal SOSCI/RP4/CN1/PMBE/RB4 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SOSCI/RP4/CN1/PMBE/RB4. Supported peripheral buses: General.
9	IO4	Digital_IO	GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
11	IO6	Digital_IO	GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12	IO7	Digital_IO	GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13	INT0/RP7/CN23/PMD5/RB7	Digital_IO	Signal terminal INT0/RP7/CN23/PMD5/RB7 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: INT0/RP7/CN23/PMD5/RB7. Supported peripheral buses: General.
14	IO16	Digital_IO	GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15	IO17	Digital_IO	GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17	VCAP	Digital_IO	Signal terminal VCAP (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
18	IO19	Digital_IO	GPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19	IO20	Digital_IO	GPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20	IO9	Digital_IO	GPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
21	IO10	Digital_IO	GPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22	IO11	Digital_IO	GPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23	IO12	Digital_IO	GPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24	AVSS	GND	0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
25	AVDD	Power_In	Primary positive power supply input (AVDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
26	MCLR#	Digital_IO	Signal terminal MCLR# (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General.
27	AN0/VREF+/CN2/RA0	Analog	Signal terminal AN0/VREF+/CN2/RA0 (Analog, 3.0V to 3.6V domain). Multiplexed alternate functions: AN0/VREF+/CN2/RA0. Supported peripheral buses: General.
28	AN1/VREF-/CN3/RA1	Analog	Signal terminal AN1/VREF-/CN3/RA1 (Analog, 3.0V to 3.6V domain). Multiplexed alternate functions: AN1/VREF-/CN3/RA1. Supported peripheral buses: General.
29	29	Digital_IO	Signal terminal 29 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: 29. Supported peripheral buses: General.

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