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PIC18F67J50-I/PT (TQFP-64(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC18F67J50-I/PT

MICROCHIPTQFP-64(10x10) · 64 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC18F67J50-I/PT (TQFP-64(10x10))1RE1/PMWR/P2C2RE0/PMRD/P2D3RG0/PMA8/ECC4RG1/PMA7/TX25RG2/PMA6/RX26RG3/PMCS1/CC7MCLR8RG4/PMCS2/CC9MCLR10IO511RF7/SS1#/C1O12RF6/AN11/C1I13RF5/AN10/C1I14RF4/D+15RF3/D-16RF2/PMA5/AN717VUSB18ENVREG19AVDD20AVSS21RA3/AN3/VREF22RA2/AN2/VREF23RA1/AN124RA0/AN025VSS26VDD27RA5/AN4/C2IN28RA4/T0CKI29RC1/T1OSI/EC30RC0/T1OSO/T131RC6/TX1/CK132RC7/RX1/DT164RE2/PMBE/P2B63RE3/PMA13/P362RE4/PMA12/P361RE5/PMA11/P160RE6/PMA10/P159RE7/PMA9/ECC58RD0/PMD057VDD56VSS55RD1/PMD154RD2/PMD253RD3/PMD352RD4/PMD4/SDO51RD5/PMD5/SDI50IO5049IO4948RB0/FLT0/INT47RB1/INT1/PMA46RB2/INT2/PMA45RB3/INT3/PMA44RB4/KBI0/PMA43RB5/KBI1/PMA42RB6/KBI2/PGC41VSS40IO4039IO3938VDD37RB7/KBI3/PGD36RC5/SDO1/C2O35RC4/SDI1/SDA34RC3/SCK1/SCL33RC2/ECCP1/P1Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=10.00mm · Pitch e=0.50mmD=10.00mm-9-7-5-3-11357997531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RE1/PMWR/P2CI/OMultiplexed I/O & Peripheral Pin RE1/PMWR/P2C (General)
2RE0/PMRD/P2DI/OMultiplexed I/O & Peripheral Pin RE0/PMRD/P2D (General)
3RG0/PMA8/ECCP3/P3AI/OMultiplexed I/O & Peripheral Pin RG0/PMA8/ECCP3/P3A (General)
4RG1/PMA7/TX2/CK2I/OMultiplexed I/O & Peripheral Pin RG1/PMA7/TX2/CK2 (General)
5RG2/PMA6/RX2/DT2I/OMultiplexed I/O & Peripheral Pin RG2/PMA6/RX2/DT2 (General)
6RG3/PMCS1/CCP4/P3DI/OMultiplexed I/O & Peripheral Pin RG3/PMCS1/CCP4/P3D (General)
7MCLRI/OMultiplexed I/O & Peripheral Pin MCLR (General)
8RG4/PMCS2/CCP5/P1DI/OMultiplexed I/O & Peripheral Pin RG4/PMCS2/CCP5/P1D (General)
9MCLRI/OMultiplexed I/O & Peripheral Pin MCLR (General)
10IO5I/OGPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4
11RF7/SS1#/C1OUTI/OMultiplexed I/O & Peripheral Pin RF7/SS1#/C1OUT (General)
12RF6/AN11/C1INAI/OMultiplexed I/O & Peripheral Pin RF6/AN11/C1INA (General)
13RF5/AN10/C1INB/CVREFI/OMultiplexed I/O & Peripheral Pin RF5/AN10/C1INB/CVREF (General)
14RF4/D+I/OMultiplexed I/O & Peripheral Pin RF4/D+ (USB)
15RF3/D-I/OMultiplexed I/O & Peripheral Pin RF3/D- (USB)
16RF2/PMA5/AN7/C2INBI/OMultiplexed I/O & Peripheral Pin RF2/PMA5/AN7/C2INB (General)
17VUSBI/OMultiplexed I/O & Peripheral Pin VUSB (USB)
18ENVREGI/OMultiplexed I/O & Peripheral Pin ENVREG (General)
19AVDDPowerPower Supply Input (AVDD — 2.0V to 3.6V)
20AVSSGNDGround Reference Pin (AVSS)
21RA3/AN3/VREF+AnalogMultiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)
22RA2/AN2/VREF-AnalogMultiplexed I/O & Peripheral Pin RA2/AN2/VREF- (General)
23RA1/AN1I/OMultiplexed I/O & Peripheral Pin RA1/AN1 (General)
24RA0/AN0I/OMultiplexed I/O & Peripheral Pin RA0/AN0 (General)
25VSSGNDGround Reference Pin (VSS)
26VDDPowerPower Supply Input (VDD — 2.0V to 3.6V)
27RA5/AN4/C2INAI/OMultiplexed I/O & Peripheral Pin RA5/AN4/C2INA (General)
28RA4/T0CKII/OMultiplexed I/O & Peripheral Pin RA4/T0CKI (General)
29RC1/T1OSI/ECCP2/P2AI/OMultiplexed I/O & Peripheral Pin RC1/T1OSI/ECCP2/P2A (General)
30RC0/T1OSO/T13CKII/OMultiplexed I/O & Peripheral Pin RC0/T1OSO/T13CKI (General)
31RC6/TX1/CK1I/OMultiplexed I/O & Peripheral Pin RC6/TX1/CK1 (General)
32RC7/RX1/DT1I/OMultiplexed I/O & Peripheral Pin RC7/RX1/DT1 (General)
33RC2/ECCP1/P1AI/OMultiplexed I/O & Peripheral Pin RC2/ECCP1/P1A (General)
34RC3/SCK1/SCL1I/OMultiplexed I/O & Peripheral Pin RC3/SCK1/SCL1 (SPI, I2C)
35RC4/SDI1/SDA1I/OMultiplexed I/O & Peripheral Pin RC4/SDI1/SDA1 (I2C)
36RC5/SDO1/C2OUTI/OMultiplexed I/O & Peripheral Pin RC5/SDO1/C2OUT (General)
37RB7/KBI3/PGDI/OMultiplexed I/O & Peripheral Pin RB7/KBI3/PGD (General)
38VDDPowerPower Supply Input (VDD — 2.0V to 3.6V)
39IO39I/OGeneral Purpose Digital I/O Pin IO39
40IO40I/OGeneral Purpose Digital I/O Pin IO40
41VSSGNDGround Reference Pin (VSS)
42RB6/KBI2/PGCI/OMultiplexed I/O & Peripheral Pin RB6/KBI2/PGC (General)
43RB5/KBI1/PMA0I/OMultiplexed I/O & Peripheral Pin RB5/KBI1/PMA0 (General)
44RB4/KBI0/PMA1I/OMultiplexed I/O & Peripheral Pin RB4/KBI0/PMA1 (General)
45RB3/INT3/PMA2I/OMultiplexed I/O & Peripheral Pin RB3/INT3/PMA2 (General)
46RB2/INT2/PMA3I/OMultiplexed I/O & Peripheral Pin RB2/INT2/PMA3 (General)
47RB1/INT1/PMA4I/OMultiplexed I/O & Peripheral Pin RB1/INT1/PMA4 (General)
48RB0/FLT0/INT0I/OMultiplexed I/O & Peripheral Pin RB0/FLT0/INT0 (General)
49IO49I/OGeneral Purpose Digital I/O Pin IO49
50IO50I/OGeneral Purpose Digital I/O Pin IO50
51RD5/PMD5/SDI2/SDA2I/OMultiplexed I/O & Peripheral Pin RD5/PMD5/SDI2/SDA2 (I2C)
52RD4/PMD4/SDO2I/OMultiplexed I/O & Peripheral Pin RD4/PMD4/SDO2 (General)
53RD3/PMD3I/OMultiplexed I/O & Peripheral Pin RD3/PMD3 (General)
54RD2/PMD2I/OMultiplexed I/O & Peripheral Pin RD2/PMD2 (General)
55RD1/PMD1I/OMultiplexed I/O & Peripheral Pin RD1/PMD1 (General)
56VSSGNDGround Reference Pin (VSS)
57VDDPowerPower Supply Input (VDD — 2.0V to 3.6V)
58RD0/PMD0I/OMultiplexed I/O & Peripheral Pin RD0/PMD0 (General)
59RE7/PMA9/ECCP2/P2AI/OMultiplexed I/O & Peripheral Pin RE7/PMA9/ECCP2/P2A (General)
60RE6/PMA10/P1BI/OMultiplexed I/O & Peripheral Pin RE6/PMA10/P1B (General)
61RE5/PMA11/P1CI/OMultiplexed I/O & Peripheral Pin RE5/PMA11/P1C (General)
62RE4/PMA12/P3BI/OMultiplexed I/O & Peripheral Pin RE4/PMA12/P3B (General)
63RE3/PMA13/P3C/REFOI/OMultiplexed I/O & Peripheral Pin RE3/PMA13/P3C/REFO (General)
64RE2/PMBE/P2BI/OMultiplexed I/O & Peripheral Pin RE2/PMBE/P2B (General)
PIN 1 RE1/PMWR/P2C
I/O
Multiplexed I/O & Peripheral Pin RE1/PMWR/P2C (General)
Design note: Signal terminal RE1/PMWR/P2C (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RE1/PMWR/P2C. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 18 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
1. Realistic 3D PackageREPRESENTATIVE
PIC18F67J50-I/PT (TQFP-64(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC18F67J50-I/PT (TQFP-64(10x10)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC18F67J50-I/PT (TQFP-64(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC18F67J50-I/PT (TQFP-64(10x10)) - 4. Package Dimensions (D×E×A)
TQFP-64(10x10) · 10.00×10.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC18F67J50-I/PT (TQFP-64(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC18F67J50-I/PT (TQFP-64(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (18 figures · Page 1/2)
Showing 1–12 of 18 uncropped original figures for PIC18F65J50 / PIC18F67J50
P2 · p02_fig011777×1640px
PIC18F67J50-I/PT (TQFP-64(10x10)) — DS39775C-page 2 © 2009 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Inc
DS39775C-page 2 © 2009 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Inc
P2 · p02_fig02788×285px
PIC18F67J50-I/PT (TQFP-64(10x10)) — DS39775C-page 2 © 2009 Microchip Technology Inc.
DS39775C-page 2 © 2009 Microchip Technology Inc.
P211 · p211_fig011777×341px
PIC18F67J50-I/PT (TQFP-64(10x10)) — FIGURE 17-2: CAPTURE MODE OPERATION BLOCK DIAGRAM
FIGURE 17-2: CAPTURE MODE OPERATION BLOCK DIAGRAM
P211 · p211_fig021777×1059px
PIC18F67J50-I/PT (TQFP-64(10x10)) — FIGURE 17-2: CAPTURE MODE OPERATION BLOCK DIAGRAM
FIGURE 17-2: CAPTURE MODE OPERATION BLOCK DIAGRAM
P212 · p212_fig011778×546px
PIC18F67J50-I/PT (TQFP-64(10x10)) — The action on the pin is based on the value of the mode select bits (CCPxM3:CCPxM0). At the same time, the interrupt flag bit, CCPxIF, is set.
The action on the pin is based on the value of the mode select bits (CCPxM3:CCPxM0). At the same time, the interrupt flag bit, CCPxIF, is set.
P212 · p212_fig021539×907px
PIC18F67J50-I/PT (TQFP-64(10x10)) — FIGURE 17-3: COMPARE MODE OPERATION BLOCK DIAGRAM
FIGURE 17-3: COMPARE MODE OPERATION BLOCK DIAGRAM
P212 · p212_fig01P212
PIC18F67J50-I/PT (TQFP-64(10x10)) — Datasheet Page 212 (p212_fig01)
Datasheet Page 212 (p212_fig01)
P237 · p237_fig011777×938px
PIC18F67J50-I/PT (TQFP-64(10x10)) — FIGURE 19-2: SPI MASTER/SLAVE CONNECTION
FIGURE 19-2: SPI MASTER/SLAVE CONNECTION
P315 · p315_fig01867×782px
PIC18F67J50-I/PT (TQFP-64(10x10)) — FIGURE 22-2: EXTERNAL CIRCUITRY PIC® Microcontroller Host Controller/HUB
FIGURE 22-2: EXTERNAL CIRCUITRY PIC® Microcontroller Host Controller/HUB
P315 · p315_fig01P315
PIC18F67J50-I/PT (TQFP-64(10x10)) — Datasheet Page 315 (p315_fig01)
Datasheet Page 315 (p315_fig01)
P459 · p459_fig01414×490px
PIC18F67J50-I/PT (TQFP-64(10x10)) — 29.1 Package Marking Information
29.1 Package Marking Information
P459 · p459_fig02414×490px
PIC18F67J50-I/PT (TQFP-64(10x10)) — Example
Example
Page 1 / 2 (18 extracted figures)

Technical Specifications & Part Details (PIC18F67J50-I/PT)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC18F67J50-I/PT (TQFP-64(10x10)) is a 64-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.20 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.0V to 3.6V supply operation across -10°C to +70°C with integrated USB, UART, SPI, I2C, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.0V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-10°C to +70°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
48 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.20 mm (A1=0.10 mm)
Package family: TQFP (TQFP-64(10x10))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-64(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TQFP-64(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC18F67J50-I/PT (TQFP-64(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC18F67J50-I/PT (TQFP-64(10x10))?

Manufactured by MICROCHIP, the PIC18F67J50-I/PT is housed in a TQFP-64(10x10) package with 64 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.0V to 3.6V. Key pins include: 1 (RE1/PMWR/P2C: Multiplexed I/O & Peripheral Pin RE1/PMWR/P2C (General)), 2 (RE0/PMRD/P2D: Multiplexed I/O & Peripheral Pin RE0/PMRD/P2D (General)), 3 (RG0/PMA8/ECCP3/P3A: Multiplexed I/O & Peripheral Pin RG0/PMA8/ECCP3/P3A (General)), 4 (RG1/PMA7/TX2/CK2: Multiplexed I/O & Peripheral Pin RG1/PMA7/TX2/CK2 (General)), 5 (RG2/PMA6/RX2/DT2: Multiplexed I/O & Peripheral Pin RG2/PMA6/RX2/DT2 (General)), 6 (RG3/PMCS1/CCP4/P3D: Multiplexed I/O & Peripheral Pin RG3/PMCS1/CCP4/P3D (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC18F67J50-I/PT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC18F67J50-I/PT (TQFP-64(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC18F67J50-I/PT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC18F67J50-I/PT (MICROCHIP, TQFP-64(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & PIC18F65J50 / PIC18F67J50 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RE1/PMWR/P2CDigital_IOSignal terminal RE1/PMWR/P2C (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RE1/PMWR/P2C. Supported peripheral buses: General.
2RE0/PMRD/P2DDigital_IOSignal terminal RE0/PMRD/P2D (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RE0/PMRD/P2D. Supported peripheral buses: General.
3RG0/PMA8/ECCP3/P3ADigital_IOSignal terminal RG0/PMA8/ECCP3/P3A (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RG0/PMA8/ECCP3/P3A. Supported peripheral buses: General.
4RG1/PMA7/TX2/CK2Digital_IOSignal terminal RG1/PMA7/TX2/CK2 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RG1/PMA7/TX2/CK2. Supported peripheral buses: General.
5RG2/PMA6/RX2/DT2Digital_IOSignal terminal RG2/PMA6/RX2/DT2 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RG2/PMA6/RX2/DT2. Supported peripheral buses: General.
6RG3/PMCS1/CCP4/P3DDigital_IOSignal terminal RG3/PMCS1/CCP4/P3D (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RG3/PMCS1/CCP4/P3D. Supported peripheral buses: General.
7MCLRDigital_IOSignal terminal MCLR (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: MCLR. Supported peripheral buses: General.
8RG4/PMCS2/CCP5/P1DDigital_IOSignal terminal RG4/PMCS2/CCP5/P1D (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RG4/PMCS2/CCP5/P1D. Supported peripheral buses: General.
9MCLRDigital_IOSignal terminal MCLR (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: MCLR. Supported peripheral buses: General.
10IO5Digital_IOGPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4
11RF7/SS1#/C1OUTRF_50OhmSignal terminal RF7/SS1#/C1OUT (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RF7/SS1#/C1OUT. Supported peripheral buses: General.
12RF6/AN11/C1INARF_50OhmSignal terminal RF6/AN11/C1INA (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RF6/AN11/C1INA. Supported peripheral buses: General.
13RF5/AN10/C1INB/CVREFRF_50OhmSignal terminal RF5/AN10/C1INB/CVREF (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RF5/AN10/C1INB/CVREF. Supported peripheral buses: General.
14RF4/D+RF_50OhmSignal terminal RF4/D+ (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RF4/D+. Supported peripheral buses: USB.
15RF3/D-RF_50OhmSignal terminal RF3/D- (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RF3/D-. Supported peripheral buses: USB.
16RF2/PMA5/AN7/C2INBRF_50OhmSignal terminal RF2/PMA5/AN7/C2INB (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RF2/PMA5/AN7/C2INB. Supported peripheral buses: General.
17VUSBDigital_IOSignal terminal VUSB (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: VUSB. Supported peripheral buses: USB.
18ENVREGDigital_IOSignal terminal ENVREG (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ENVREG. Supported peripheral buses: General.
19AVDDPower_InPrimary positive power supply input (AVDD) operating in the 2.0V to 3.6V domain (Max rating: 3.6V).
20AVSSGND0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
21RA3/AN3/VREF+AnalogSignal terminal RA3/AN3/VREF+ (Analog, 2.0V to 3.6V domain). Multiplexed alternate functions: RA3/AN3/VREF+. Supported peripheral buses: General.
22RA2/AN2/VREF-AnalogSignal terminal RA2/AN2/VREF- (Analog, 2.0V to 3.6V domain). Multiplexed alternate functions: RA2/AN2/VREF-. Supported peripheral buses: General.
23RA1/AN1Digital_IOSignal terminal RA1/AN1 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RA1/AN1. Supported peripheral buses: General.
24RA0/AN0Digital_IOSignal terminal RA0/AN0 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RA0/AN0. Supported peripheral buses: General.
25VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
26VDDPower_InPrimary positive power supply input (VDD) operating in the 2.0V to 3.6V domain (Max rating: 3.6V).
27RA5/AN4/C2INADigital_IOSignal terminal RA5/AN4/C2INA (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RA5/AN4/C2INA. Supported peripheral buses: General.
28RA4/T0CKIDigital_IOSignal terminal RA4/T0CKI (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RA4/T0CKI. Supported peripheral buses: General.
29RC1/T1OSI/ECCP2/P2ADigital_IOSignal terminal RC1/T1OSI/ECCP2/P2A (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RC1/T1OSI/ECCP2/P2A. Supported peripheral buses: General.
30RC0/T1OSO/T13CKIDigital_IOSignal terminal RC0/T1OSO/T13CKI (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RC0/T1OSO/T13CKI. Supported peripheral buses: General.
31RC6/TX1/CK1Digital_IOSignal terminal RC6/TX1/CK1 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RC6/TX1/CK1. Supported peripheral buses: General.
32RC7/RX1/DT1Digital_IOSignal terminal RC7/RX1/DT1 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RC7/RX1/DT1. Supported peripheral buses: General.
33RC2/ECCP1/P1ADigital_IOSignal terminal RC2/ECCP1/P1A (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RC2/ECCP1/P1A. Supported peripheral buses: General.
34RC3/SCK1/SCL1Digital_IOSignal terminal RC3/SCK1/SCL1 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RC3/SCK1/SCL1. Supported peripheral buses: SPI, I2C.
35RC4/SDI1/SDA1Digital_IOSignal terminal RC4/SDI1/SDA1 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RC4/SDI1/SDA1. Supported peripheral buses: I2C.
36RC5/SDO1/C2OUTDigital_IOSignal terminal RC5/SDO1/C2OUT (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RC5/SDO1/C2OUT. Supported peripheral buses: General.
37RB7/KBI3/PGDDigital_IOSignal terminal RB7/KBI3/PGD (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RB7/KBI3/PGD. Supported peripheral buses: General.
38VDDPower_InPrimary positive power supply input (VDD) operating in the 2.0V to 3.6V domain (Max rating: 3.6V).
39IO39Digital_IOGeneral Purpose Digital I/O Pin IO39
40IO40Digital_IOGeneral Purpose Digital I/O Pin IO40
41VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
42RB6/KBI2/PGCDigital_IOSignal terminal RB6/KBI2/PGC (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RB6/KBI2/PGC. Supported peripheral buses: General.
43RB5/KBI1/PMA0Digital_IOSignal terminal RB5/KBI1/PMA0 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RB5/KBI1/PMA0. Supported peripheral buses: General.
44RB4/KBI0/PMA1Digital_IOSignal terminal RB4/KBI0/PMA1 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RB4/KBI0/PMA1. Supported peripheral buses: General.
45RB3/INT3/PMA2Digital_IOSignal terminal RB3/INT3/PMA2 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RB3/INT3/PMA2. Supported peripheral buses: General.
46RB2/INT2/PMA3Digital_IOSignal terminal RB2/INT2/PMA3 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RB2/INT2/PMA3. Supported peripheral buses: General.
47RB1/INT1/PMA4Digital_IOSignal terminal RB1/INT1/PMA4 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RB1/INT1/PMA4. Supported peripheral buses: General.
48RB0/FLT0/INT0Digital_IOSignal terminal RB0/FLT0/INT0 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RB0/FLT0/INT0. Supported peripheral buses: General.
49IO49Digital_IOGeneral Purpose Digital I/O Pin IO49
50IO50Digital_IOGeneral Purpose Digital I/O Pin IO50
51RD5/PMD5/SDI2/SDA2Digital_IOSignal terminal RD5/PMD5/SDI2/SDA2 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RD5/PMD5/SDI2/SDA2. Supported peripheral buses: I2C.
52RD4/PMD4/SDO2Digital_IOSignal terminal RD4/PMD4/SDO2 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RD4/PMD4/SDO2. Supported peripheral buses: General.
53RD3/PMD3Digital_IOSignal terminal RD3/PMD3 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RD3/PMD3. Supported peripheral buses: General.
54RD2/PMD2Digital_IOSignal terminal RD2/PMD2 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RD2/PMD2. Supported peripheral buses: General.
55RD1/PMD1Digital_IOSignal terminal RD1/PMD1 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RD1/PMD1. Supported peripheral buses: General.
56VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
57VDDPower_InPrimary positive power supply input (VDD) operating in the 2.0V to 3.6V domain (Max rating: 3.6V).
58RD0/PMD0Digital_IOSignal terminal RD0/PMD0 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RD0/PMD0. Supported peripheral buses: General.
59RE7/PMA9/ECCP2/P2ADigital_IOSignal terminal RE7/PMA9/ECCP2/P2A (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RE7/PMA9/ECCP2/P2A. Supported peripheral buses: General.
60RE6/PMA10/P1BDigital_IOSignal terminal RE6/PMA10/P1B (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RE6/PMA10/P1B. Supported peripheral buses: General.
61RE5/PMA11/P1CDigital_IOSignal terminal RE5/PMA11/P1C (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RE5/PMA11/P1C. Supported peripheral buses: General.
62RE4/PMA12/P3BDigital_IOSignal terminal RE4/PMA12/P3B (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RE4/PMA12/P3B. Supported peripheral buses: General.
63RE3/PMA13/P3C/REFODigital_IOSignal terminal RE3/PMA13/P3C/REFO (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RE3/PMA13/P3C/REFO. Supported peripheral buses: General.
64RE2/PMBE/P2BDigital_IOSignal terminal RE2/PMBE/P2B (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RE2/PMBE/P2B. Supported peripheral buses: General.
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