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AT27C020-55JU (PLCC-32(11.4x14)) — Symbol, Footprint IPC-7351B & 3D STEP Model

AT27C020-55JU

MICROCHIPPLCC-32(11.4x14) · 32 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · AT27C020-55JU (PLCC-32(11.4x14))1VPP2A163A154A125A76A67A58A49A310A211A112A013O014O115O216GND32VCC31#PGM30A1729A1428A1327A826A925A1124#OE23A1022#CE21O720O619O518O417O3Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.825.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
3231301234292827262524232221201918171615141312111098765E=11.40mm · Pitch e=1.27mmD=14.00mm-11-9-7-5-3-11357911121086420-2-4-6-8-10-12mm
3. 3D CAD MODEL
Package Body: 11.40mm × 14.00mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (32/32)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VPPI/OMultiplexed I/O & Peripheral Pin VPP (General)
2A16I/OMultiplexed I/O & Peripheral Pin A16 (General)
3A15I/OMultiplexed I/O & Peripheral Pin A15 (General)
4A12I/OMultiplexed I/O & Peripheral Pin A12 (General)
5A7I/OMultiplexed I/O & Peripheral Pin A7 (General)
6A6I/OMultiplexed I/O & Peripheral Pin A6 (General)
7A5I/OMultiplexed I/O & Peripheral Pin A5 (General)
8A4I/OMultiplexed I/O & Peripheral Pin A4 (General)
9A3I/OMultiplexed I/O & Peripheral Pin A3 (General)
10A2I/OMultiplexed I/O & Peripheral Pin A2 (General)
11A1I/OMultiplexed I/O & Peripheral Pin A1 (General)
12A0I/OMultiplexed I/O & Peripheral Pin A0 (General)
13O0I/OMultiplexed I/O & Peripheral Pin O0 (General)
14O1I/OMultiplexed I/O & Peripheral Pin O1 (General)
15O2I/OMultiplexed I/O & Peripheral Pin O2 (General)
16GNDGNDGround Reference Pin (GND)
17O3I/OMultiplexed I/O & Peripheral Pin O3 (General)
18O4I/OMultiplexed I/O & Peripheral Pin O4 (General)
19O5I/OMultiplexed I/O & Peripheral Pin O5 (General)
20O6I/OMultiplexed I/O & Peripheral Pin O6 (General)
21O7I/OMultiplexed I/O & Peripheral Pin O7 (General)
22#CEI/OMultiplexed I/O & Peripheral Pin #CE (General)
23A10I/OMultiplexed I/O & Peripheral Pin A10 (General)
24#OEI/OMultiplexed I/O & Peripheral Pin #OE (General)
25A11I/OMultiplexed I/O & Peripheral Pin A11 (General)
26A9I/OMultiplexed I/O & Peripheral Pin A9 (General)
27A8I/OMultiplexed I/O & Peripheral Pin A8 (General)
28A13I/OMultiplexed I/O & Peripheral Pin A13 (General)
29A14I/OMultiplexed I/O & Peripheral Pin A14 (General)
30A17I/OMultiplexed I/O & Peripheral Pin A17 (General)
31#PGMI/OMultiplexed I/O & Peripheral Pin #PGM (General)
32VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
PIN 1 VPP
I/O
Multiplexed I/O & Peripheral Pin VPP (General)
Design note: Signal terminal VPP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VPP. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
1. Realistic 3D PackageREPRESENTATIVE
AT27C020-55JU (PLCC-32(11.4x14)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
AT27C020-55JU (PLCC-32(11.4x14)) - 2. Standard Pinout (Top View)
True package pinout (32 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
AT27C020-55JU (PLCC-32(11.4x14)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
AT27C020-55JU (PLCC-32(11.4x14)) - 4. Package Dimensions (D×E×A)
PLCC-32(11.4x14) · 11.40×14.00mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
AT27C020-55JU (PLCC-32(11.4x14)) - 5. Recommended Land Pattern
IPC-7351B Footprint (32 Pads)Expand ›
6. Application SchematicSCHEMATIC
AT27C020-55JU (PLCC-32(11.4x14)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for AT27C020
P1 · p01_fig01646×390px
AT27C020-55JU (PLCC-32(11.4x14)) — 2Mb (256K x 8) One-time Programmable, Read-only Memory
2Mb (256K x 8) One-time Programmable, Read-only Memory
P1 · p01_fig02392×282px
AT27C020-55JU (PLCC-32(11.4x14)) — = ANMEL
= ANMEL
P2 · p02_fig01434×754px
AT27C020-55JU (PLCC-32(11.4x14)) — 3. System considerations
3. System considerations
P2 · p02_fig031212×611px
AT27C020-55JU (PLCC-32(11.4x14)) — Figure 3-1. Block diagram
Figure 3-1. Block diagram
P11 · p11_fig012128×2823px
AT27C020-55JU (PLCC-32(11.4x14)) — 11 | 0570H-EPROM-4/11 | Atmel AT27C020 | 8. Packaging information | 32J - PLCC | DRAWING NO. REV. TITLE | 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B 32J | 10/04/01 | 1.14(0.045) X 45° PIN NO. 1 IDENTIFIER | 1.14(0.045) X 45° | 0.5
11 | 0570H-EPROM-4/11 | Atmel AT27C020 | 8. Packaging information | 32J - PLCC | DRAWING NO. REV. TITLE | 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B 32J | 10/04/01 | 1.14(0.045) X 45° PIN NO. 1 IDENTIFIER | 1.14(0.045) X 45° | 0.5
P11 · p11_fig01P11
AT27C020-55JU (PLCC-32(11.4x14)) — Datasheet Page 11 (p11_fig01)
Datasheet Page 11 (p11_fig01)
P2 · p02_fig02All Packages in PDF
AT27C020-55JU (PLCC-32(11.4x14)) — 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 | 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 | VPP | A16 A15 A12 | A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND | VCC PGM A17 A14 A13 A8 A9 A11 OE A10 CE 07 06 05 04 03 | 32-lead PDIP Top view
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 | 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 | VPP | A16 A15 A12 | A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND | VCC PGM A17 A14 A13 A8 A9 A11 OE A10 CE 07 06 05 04 03 | 32-lead PDIP Top view
P12 · p12_fig01All Packages in PDF
AT27C020-55JU (PLCC-32(11.4x14)) — 32P6 - PDIP | TITLE DRAWING NO. REV. Package Drawing Contact: packagedrawings@atmel.com 32P6, 32-lead (0.600"/15.24mm wide) Plastic Dual Inline Package (PDIP) B 32P6 | 09/28/01 | PIN | 1 | E1 | A1 | B | REF | E | B1 | C | L | SEATING PLANE
32P6 - PDIP | TITLE DRAWING NO. REV. Package Drawing Contact: packagedrawings@atmel.com 32P6, 32-lead (0.600"/15.24mm wide) Plastic Dual Inline Package (PDIP) B 32P6 | 09/28/01 | PIN | 1 | E1 | A1 | B | REF | E | B1 | C | L | SEATING PLANE
P10 · p10_fig012040×2545px
AT27C020-55JU (PLCC-32(11.4x14)) — PACKAGE_DIMENSIONS — AT27C020-15TC (TSOP-32)
PACKAGE_DIMENSIONS — AT27C020-15TC (TSOP-32)

Technical Specifications & Part Details (AT27C020-55JU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:AT27C020-55JU (PLCC-32(11.4x14)) is a 32-pin standard electronic & interconnect component featuring a 14.00 × 11.40 × 1.15 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -55°C to +125°C with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-55°C to +125°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
5MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
14.00 × 11.40 × 1.15 mm (A1=0.03 mm)
Package family: LGA (PLCC-32(11.4x14))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol32 auto-grouped pins
OK
IPC-7351B Land Pattern32 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — AT27C020 (4)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (PLCC-32(11.4x14))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
14.00 × 11.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.15mm · e=1.27mm
Pad Size (W × L)Level B
0.62 × 2.40 mm
Pins / Total PadsTopology
32P / 32Pad (LGA_ARRAY)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PLCC-32(11.4x14)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT27C020-55JU (PLCC-32(11.4x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT27C020-55JU (PLCC-32(11.4x14))?

Manufactured by MICROCHIP, the AT27C020-55JU is housed in a PLCC-32(11.4x14) package with 32 pins and a 1.27 mm lead pitch. Key pins include: 1 (VPP: Multiplexed I/O & Peripheral Pin VPP (General)), 2 (A16: Multiplexed I/O & Peripheral Pin A16 (General)), 3 (A15: Multiplexed I/O & Peripheral Pin A15 (General)), 4 (A12: Multiplexed I/O & Peripheral Pin A12 (General)), 5 (A7: Multiplexed I/O & Peripheral Pin A7 (General)), 6 (A6: Multiplexed I/O & Peripheral Pin A6 (General)).

What are the IPC-7351B PCB Footprint dimensions for AT27C020-55JU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT27C020-55JU (PLCC-32(11.4x14)) has a nominal body envelope of 11.40 × 14.00 mm, pitch e = 1.27 mm, and 32 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT27C020-55JU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT27C020-55JU (MICROCHIP, PLCC-32(11.4x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (32 pins) & AT27C020 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VPPDigital_IOSignal terminal VPP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VPP. Supported peripheral buses: General.
2A16Digital_IOSignal terminal A16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A16. Supported peripheral buses: General.
3A15Digital_IOSignal terminal A15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A15. Supported peripheral buses: General.
4A12Digital_IOSignal terminal A12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A12. Supported peripheral buses: General.
5A7Digital_IOSignal terminal A7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A7. Supported peripheral buses: General.
6A6Digital_IOSignal terminal A6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A6. Supported peripheral buses: General.
7A5Digital_IOSignal terminal A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A5. Supported peripheral buses: General.
8A4Digital_IOSignal terminal A4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A4. Supported peripheral buses: General.
9A3Digital_IOSignal terminal A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3. Supported peripheral buses: General.
10A2Digital_IOSignal terminal A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
11A1Digital_IOSignal terminal A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
12A0Digital_IOSignal terminal A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
13O0Digital_IOSignal terminal O0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O0. Supported peripheral buses: General.
14O1Digital_IOSignal terminal O1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O1. Supported peripheral buses: General.
15O2Digital_IOSignal terminal O2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O2. Supported peripheral buses: General.
16GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
17O3Digital_IOSignal terminal O3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O3. Supported peripheral buses: General.
18O4Digital_IOSignal terminal O4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O4. Supported peripheral buses: General.
19O5Digital_IOSignal terminal O5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O5. Supported peripheral buses: General.
20O6Digital_IOSignal terminal O6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O6. Supported peripheral buses: General.
21O7Digital_IOSignal terminal O7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O7. Supported peripheral buses: General.
22#CEDigital_IOSignal terminal #CE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: #CE. Supported peripheral buses: General.
23A10Digital_IOSignal terminal A10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A10. Supported peripheral buses: General.
24#OEDigital_IOSignal terminal #OE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: #OE. Supported peripheral buses: General.
25A11Digital_IOSignal terminal A11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A11. Supported peripheral buses: General.
26A9Digital_IOSignal terminal A9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A9. Supported peripheral buses: General.
27A8Digital_IOSignal terminal A8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A8. Supported peripheral buses: General.
28A13Digital_IOSignal terminal A13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A13. Supported peripheral buses: General.
29A14Digital_IOSignal terminal A14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A14. Supported peripheral buses: General.
30A17Digital_IOSignal terminal A17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A17. Supported peripheral buses: General.
31#PGMDigital_IOSignal terminal #PGM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: #PGM. Supported peripheral buses: General.
32VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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