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STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F412RGY6PTR

STID: C2055542WLCSP-64(3.6x3.6) · 64 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F412RGY6PTR (WLCSP-64(3.6x3.6))A1VDDA2PA15A3PC12A4PD2A5PB3A6PB7A7VSSA8VDDB1VSSB2PA14B3PC11B4PB4B5PB6B6PB9B7VBATB8PC13C1PA12C2PA13C3PC10C4PB5C5PB8C6PDR_ONC7PC15 - OSC32C8PC14 - OSC32D1PA9D2PD2D3PA11D4BOOT0D5PC0D6PC3D7NRSTD8PH0 - OSC_INH8PA2H7VDDH6PA6H5PB0H4PB10H3VCAP_1H2VSSH1VDDG8VSSA/ VREFG7PA1G6PA4G5PC5G4PB2G3PB12G2PB13G1PB14F8PC1F7VDDA/ VREF+F6PA3F5PA5F4PB1F3PC8F2PB15F1PC6E8PH1 - OSC_OUE7PC2E6PA0E5PA7E4PC4E3PA8E2PC9E1PC7Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1A2B2C2D2E2F2G2H2A3B3C3D3E3F3G3H3A4B4C4D4E4F4G4H4A5B5C5D5E5F5G5H5A6B6C6D6E6F6G6H6A7B7C7D7E7F7G7H7A8B8C8D8E8F8G8H8E=3.60mm · Pitch e=0.40mmD=3.60mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.60mm × 3.60mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
A2PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
A3PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
A4PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
A5PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
A6PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
A7VSSGNDGround Reference Pin (VSS)
A8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
B1VSSGNDGround Reference Pin (VSS)
B2PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
B3PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
B4PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
B6PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
B7VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B8PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
C1PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
C2PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
C3PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
C4PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
C5PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
C6PDR_ONI/OMultiplexed I/O & Peripheral Pin PDR_ON (General)
C7PC15 - OSC32_ OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_ OUT (RTC/CLK)
C8PC14 - OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK)
D1PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
D2PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
D3PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
D4BOOT0IInput-Only Pin BOOT0 (General)
D5PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
D6PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI, ADC)
D7NRSTISystem Enable & Hardware Reset (NRST)
D8PH0 - OSC_INI/OMultiplexed I/O & Peripheral Pin PH0 - OSC_IN (RTC/CLK)
E1PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
E2PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E3PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
E4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
E5PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
E6PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM)
E7PC2I/OMultiplexed I/O & Peripheral Pin PC2 (SPI, ADC)
E8PH1 - OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1 - OSC_OUT (RTC/CLK)
F1PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
F2PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
F3PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
F4PB1I/OMultiplexed I/O & Peripheral Pin PB1 (SPI, ADC, PWM)
F5PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
F6PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
F7VDDA/ VREF+PowerPower Supply Input (VDDA/ VREF+ — 3.3V VDD (Max 4.0V))
F8PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
G1PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
G2PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
G3PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
G4PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
G5PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, I2C, ADC)
G6PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
G7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, SPI, ADC, PWM)
G8VSSA/ VREFGNDGround Reference Pin (VSSA/ VREF)
H1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
H2VSSGNDGround Reference Pin (VSS)
H3VCAP_1I/OMultiplexed I/O & Peripheral Pin VCAP_1 (General)
H4PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
H5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (SPI, ADC, PWM)
H6PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
H7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
H8PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
PIN A1 VDD
Power
Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F412RGY6PTR (ST · WLCSP-64(3.6x3.6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) - 4. Package Dimensions (D×E×A)
WLCSP-64(3.6x3.6) · 3.60×3.60mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for STM32F412
P1 · p01_fig01EXACT PACKAGE
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) — Arm®-Cortex®-M4 32b MCU+FPU, 125 DMIPS, 1MB Flash, 256KB RAM, USB OTG FS, 17 TIMs, 1 ADC, 17 comm. interfaces | Datasheet - production data | WLCSP64 | )%*$ | UFQFPN48 | (7x7 mm) | UFBGA100 | (7x7mm) UFBGA144 (10x10mm) (3.623x3.651mm) LQFP1
Arm®-Cortex®-M4 32b MCU+FPU, 125 DMIPS, 1MB Flash, 256KB RAM, USB OTG FS, 17 TIMs, 1 ADC, 17 comm. interfaces | Datasheet - production data | WLCSP64 | )%*$ | UFQFPN48 | (7x7 mm) | UFBGA100 | (7x7mm) UFBGA144 (10x10mm) (3.623x3.651mm) LQFP1
P43 · p43_fig01EXACT PACKAGE
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) — Figure 11. STM32F412xE/G WLCSP64 pinout
Figure 11. STM32F412xE/G WLCSP64 pinout
P167 · p167_fig01EXACT PACKAGE
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) — Figure 60. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
Figure 60. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
P168 · p168_fig01EXACT PACKAGE
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) — Figure 61. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
Figure 61. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
P169 · p169_fig01EXACT PACKAGE
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) — Figure 62. WLCSP64 marking example (package top view)
Figure 62. WLCSP64 marking example (package top view)
P43 · p43_fig01P43
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) — Datasheet Page 43 (p43_fig01)
Datasheet Page 43 (p43_fig01)
P145 · p145_fig011751×831px
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) — Figure 47. Typical connection diagram using the ADC
Figure 47. Typical connection diagram using the ADC
P145 · p145_fig01P145
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) — Datasheet Page 145 (p145_fig01)
Datasheet Page 145 (p145_fig01)
P168 · p168_fig01P168
STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) — Datasheet Page 168 (p168_fig01)
Datasheet Page 168 (p168_fig01)

Technical Specifications & Part Details (STM32F412RGY6PTR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) is a 64-pin embedded microcontroller unit (mcu) featuring a 3.60 × 3.60 × 0.56 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.7 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, CAN, ADC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.7 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
100 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
22 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
3.60 × 3.60 × 0.56 mm (A1=0.17 mm)
Package family: WLCSP (WLCSP-64(3.6x3.6))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, CAN, ADC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PB2): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-64(3.6x3.6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.60 × 3.60 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
64P / 64Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-64(3.6x3.6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F412RGY6PTR (WLCSP-64(3.6x3.6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F412RGY6PTR (WLCSP-64(3.6x3.6))?

Manufactured by ST, the STM32F412RGY6PTR is housed in a WLCSP-64(3.6x3.6) package with 64 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: A1 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), A2 (PA15: Multiplexed I/O & Peripheral Pin PA15 (General)), A3 (PC12: Multiplexed I/O & Peripheral Pin PC12 (General)), A4 (PD2: Multiplexed I/O & Peripheral Pin PD2 (General)), A5 (PB3: Multiplexed I/O & Peripheral Pin PB3 (General)), A6 (PB7: Multiplexed I/O & Peripheral Pin PB7 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32F412RGY6PTR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F412RGY6PTR (WLCSP-64(3.6x3.6)) has a nominal body envelope of 3.60 × 3.60 mm, pitch e = 0.40 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F412RGY6PTR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F412RGY6PTR (ST, WLCSP-64(3.6x3.6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & STM32F412 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A2PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
A3PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
A4PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
A5PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
A6PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
A7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
A8VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B2PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
B3PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
B4PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
B6PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
B7VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B8PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
C1PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
C2PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
C3PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
C4PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
C5PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
C6PDR_ONDigital_IOSignal terminal PDR_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General.
C7PC15 - OSC32_ OUTDigital_IOSignal terminal PC15 - OSC32_ OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15 - OSC32_ OUT. Supported peripheral buses: RTC/CLK.
C8PC14 - OSC32_INDigital_IOSignal terminal PC14 - OSC32_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN. Supported peripheral buses: RTC/CLK.
D1PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
D2PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
D3PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
D4BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
D5PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
D6PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC.
D7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
D8PH0 - OSC_INDigital_IOSignal terminal PH0 - OSC_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC_IN. Supported peripheral buses: RTC/CLK.
E1PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
E2PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E3PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
E4PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
E5PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
E6PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM.
E7PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, ADC.
E8PH1 - OSC_OUTDigital_IOSignal terminal PH1 - OSC_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC_OUT. Supported peripheral buses: RTC/CLK.
F1PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
F2PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
F3PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
F4PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI5_NSS. Supported peripheral buses: SPI, ADC, PWM.
F5PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, PWM.
F6PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
F7VDDA/ VREF+Power_InPrimary positive power supply input (VDDA/ VREF+) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F8PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
G1PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
G2PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
G3PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
G4PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
G5PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: UART, I2C, ADC.
G6PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, ADC.
G7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MOSI. Supported peripheral buses: UART, SPI, ADC, PWM.
G8VSSA/ VREFGND0V electrical ground return terminal (VSSA/ VREF) for internal core logic, I/O drivers, and analog sub-blocks.
H1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
H2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
H3VCAP_1Digital_IOSignal terminal VCAP_1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_1. Supported peripheral buses: General.
H4PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
H5PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI5_SCK. Supported peripheral buses: SPI, ADC, PWM.
H6PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOI2S2MCK. Supported peripheral buses: SPI, ADC.
H7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
H8PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
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