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STM32F302VCY6TR (WLCSP-100(4.2x4.7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F302VCY6TR

STID: C2055199WLCSP-100(4.2x4.7) · 100 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F302VCY6TR (WLCSP-100(4.2x4.7))A1VSSA2VSSA3PC12A4PD2A5PB3A6PB5A7BOOT0A8PE1A9VDDA10VDDB1VSSB2PA15B3PD0B4PD3B5PB4B6PB6B7PE0B8VDDB9PE5B10VDDC1PF6C2PA14C3PD1C4PD4C5PB7C6PB9C7VSSC8PE4C9PC13C10IOC10D1PA12D2VDDD3PC11D4PD7D5PB8D6PE2D7PE3D8VBATD9IOD9D10PF9E1PA10E2PA11E3PA13E4PC10E5PA9E6PE8E7PE6E8PF2E9NRSTE10PF10K10VSSK9VSSK8VDDK7PA7K6PB1K5PB2K4PB10K3PB11K2VSSK1VSSJ10VDDAJ9PA1J8VREF+J7PA4J6PB0J5VDDJ4PB12J3PB13J2PB14J1VSSH10PC3H9PA0H8VSSA/ VREF -H7PA5H6PA6H5PE11H4PB15H3PD10H2PD11H1PD12G10PC0G9PC1G8PC2G7PA3G6PC4G5PE12G4PD9G3PD13G2PD14G1PD15F10PF0 - OSC_INF9PF1 - OSC_OUF8PE7F7PA2F6PC5F5PA8F4PC6F3PC9F2PC7F1PC8Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1A2B2C2D2E2F2G2H2J2K2A3B3C3D3E3F3G3H3J3K3A4B4C4D4E4F4G4H4J4K4A5B5C5D5E5F5G5H5J5K5A6B6C6D6E6F6G6H6J6K6A7B7C7D7E7F7G7H7J7K7A8B8C8D8E8F8G8H8J8K8A9B9C9D9E9F9G9H9J9K9A10B10C10D10E10F10G10H10J10K10E=4.20mm · Pitch e=0.40mmD=4.70mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.20mm × 4.70mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VSSGNDGround Reference Pin (VSS)
A2VSSGNDGround Reference Pin (VSS)
A3PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI)
A4PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
A5PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI, PWM, SWD/JTAG)
A6PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI, PWM)
A7BOOT0IInput-Only Pin BOOT0 (General)
A8PE1I/OMultiplexed I/O & Peripheral Pin PE1 (UART)
A9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
A10VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
B1VSSGNDGround Reference Pin (VSS)
B2PA15I/OMultiplexed I/O & Peripheral Pin PA15 (UART, SPI, I2C, PWM)
B3PD0I/OMultiplexed I/O & Peripheral Pin PD0 (CAN)
B4PD3I/OMultiplexed I/O & Peripheral Pin PD3 (UART, PWM)
B5PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, PWM, SWD/JTAG)
B6PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C)
B7PE0I/OMultiplexed I/O & Peripheral Pin PE0 (UART)
B8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
B9PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
B10VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
C1PF6I/OMultiplexed I/O & Peripheral Pin PF6 (UART, I2C, PWM)
C2PA14I/OMultiplexed I/O & Peripheral Pin PA14 (UART, I2C)
C3PD1I/OMultiplexed I/O & Peripheral Pin PD1 (CAN)
C4PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART, PWM)
C5PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C, PWM)
C6PB9I/OMultiplexed I/O & Peripheral Pin PB9 (I2C)
C7VSSGNDGround Reference Pin (VSS)
C8PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
C9PC13I/OMultiplexed I/O & Peripheral Pin PC13 (PWM, RTC/CLK)
C10IOC10I/OGeneral Purpose Digital I/O Pin IOC10
D1PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART, CAN)
D2VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D3PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI)
D4PD7I/OMultiplexed I/O & Peripheral Pin PD7 (UART)
D5PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
D6PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
D7PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
D8VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
D9IOD9I/OGeneral Purpose Digital I/O Pin IOD9
D10PF9I/OMultiplexed I/O & Peripheral Pin PF9 (General)
E1PA10I/OMultiplexed I/O & Peripheral Pin PA10 (I2C, PWM)
E2PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, PWM, CAN)
E3PA13I/OMultiplexed I/O & Peripheral Pin PA13 (UART)
E4PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
E5PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C, PWM)
E6PE8I/OMultiplexed I/O & Peripheral Pin PE8 (PWM)
E7PE6I/OMultiplexed I/O & Peripheral Pin PE6 (RTC/CLK)
E8PF2I/OMultiplexed I/O & Peripheral Pin PF2 (ADC)
E9NRSTISystem Enable & Hardware Reset (NRST)
E10PF10I/OMultiplexed I/O & Peripheral Pin PF10 (General)
F1PC8I/OMultiplexed I/O & Peripheral Pin PC8 (PWM)
F2PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
F3PC9I/OMultiplexed I/O & Peripheral Pin PC9 (PWM)
F4PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
F5PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, I2C)
F6PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
F7PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC)
F8PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
F9PF1 - OSC_OUT (PF1)I/OMultiplexed I/O & Peripheral Pin PF1 - OSC_OUT (PF1) (I2C, RTC/CLK)
F10PF0 - OSC_IN (PF0)I/OMultiplexed I/O & Peripheral Pin PF0 - OSC_IN (PF0) (PWM, RTC/CLK)
G1PD15I/OMultiplexed I/O & Peripheral Pin PD15 (SPI)
G2PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
G3PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
G4PD9I/OMultiplexed I/O & Peripheral Pin PD9 (UART)
G5PE12I/OMultiplexed I/O & Peripheral Pin PE12 (PWM)
G6PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
G7PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC)
G8PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
G9PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
G10PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
H1PD12I/OMultiplexed I/O & Peripheral Pin PD12 (UART)
H2PD11I/OMultiplexed I/O & Peripheral Pin PD11 (UART)
H3PD10I/OMultiplexed I/O & Peripheral Pin PD10 (UART)
H4PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM)
H5PE11I/OMultiplexed I/O & Peripheral Pin PE11 (PWM)
H6PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
H7PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
H8VSSA/ VREF -GNDGround Reference Pin (VSSA/ VREF -)
H9PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
H10PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
J1VSSGNDGround Reference Pin (VSS)
J2PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
J3PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI)
J4PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI)
J5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
J6PB0I/OMultiplexed I/O & Peripheral Pin PB0 (PWM)
J7PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, PWM)
J8VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
J9PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
J10VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
K1VSSGNDGround Reference Pin (VSS)
K2VSSGNDGround Reference Pin (VSS)
K3PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART)
K4PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART)
K5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (ADC)
K6PB1I/OMultiplexed I/O & Peripheral Pin PB1 (PWM)
K7PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
K8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
K9VSSGNDGround Reference Pin (VSS)
K10VSSGNDGround Reference Pin (VSS)
PIN A1 VSS
GND
Ground Reference Pin (VSS)
Design note: Alt: Ground
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F302VCY6TR (ST · WLCSP-100(4.2x4.7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) - 4. Package Dimensions (D×E×A)
WLCSP-100(4.2x4.7) · 4.20×4.70mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for STM32F302
P35 · p35_fig01EXACT PACKAGE
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) — Figure 7. STM32F302xB/STM32F302xC WLCSP100 pinout
Figure 7. STM32F302xB/STM32F302xC WLCSP100 pinout
P136 · p136_fig01EXACT PACKAGE
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) — Figure 49. WLCSP100 - 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
Figure 49. WLCSP100 - 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
P143 · p143_fig01EXACT PACKAGE
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) — STM32F302xB STM32F302xC Revision history
STM32F302xB STM32F302xC Revision history
P1 · p01_fig01881×626px
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) — • Up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensors
• Up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensors
P35 · p35_fig01P35
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) — Datasheet Page 35 (p35_fig01)
Datasheet Page 35 (p35_fig01)
P116 · p116_fig011751×913px
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) — Figure 34. ADC accuracy characteristics
Figure 34. ADC accuracy characteristics
P116 · p116_fig021546×754px
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) — Figure 35. Typical connection diagram using the ADC
Figure 35. Typical connection diagram using the ADC
P116 · p116_fig01P116
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) — Datasheet Page 116 (p116_fig01)
Datasheet Page 116 (p116_fig01)
P126 · p126_fig011546×1093px
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) — Figure 40. LQFP100 - 14 x 14 mm, low-profile quad flat package recommended
Figure 40. LQFP100 - 14 x 14 mm, low-profile quad flat package recommended
P136 · p136_fig01P136
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) — Datasheet Page 136 (p136_fig01)
Datasheet Page 136 (p136_fig01)
P143 · p143_fig01P143
STM32F302VCY6TR (WLCSP-100(4.2x4.7)) — Datasheet Page 143 (p143_fig01)
Datasheet Page 143 (p143_fig01)

Technical Specifications & Part Details (STM32F302VCY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F302VCY6TR (WLCSP-100(4.2x4.7)) is a 100-pin embedded microcontroller unit (mcu) featuring a 4.70 × 4.20 × 0.56 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 2.0 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, IrDA, CAN, RTC/CLK, SPI, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
2.0 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
72 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
40 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
4.70 × 4.20 × 0.56 mm (A1=0.17 mm)
Package family: WLCSP (WLCSP-100(4.2x4.7))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, IrDA, CAN, RTC/CLK, SPI, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-100(4.2x4.7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.70 × 4.20 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-100(4.2x4.7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F302VCY6TR (WLCSP-100(4.2x4.7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F302VCY6TR (WLCSP-100(4.2x4.7))?

Manufactured by ST, the STM32F302VCY6TR is housed in a WLCSP-100(4.2x4.7) package with 100 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 2.0 V to 3.6 V. Key pins include: A1 (VSS: Ground Reference Pin (VSS)), A2 (VSS: Ground Reference Pin (VSS)), A3 (PC12: Multiplexed I/O & Peripheral Pin PC12 (UART, SPI)), A4 (PD2: Multiplexed I/O & Peripheral Pin PD2 (UART)), A5 (PB3: Multiplexed I/O & Peripheral Pin PB3 (SPI, PWM, SWD/JTAG)), A6 (PB5: Multiplexed I/O & Peripheral Pin PB5 (UART, SPI, PWM)).

What are the IPC-7351B PCB Footprint dimensions for STM32F302VCY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F302VCY6TR (WLCSP-100(4.2x4.7)) has a nominal body envelope of 4.20 × 4.70 mm, pitch e = 0.40 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F302VCY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F302VCY6TR (ST, WLCSP-100(4.2x4.7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32F302 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
A2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
A3PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSII2S3SD. Supported peripheral buses: UART, SPI.
A4PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
A5PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCKI2S3CK, SPI1_SCKUSART2TX. Supported peripheral buses: SPI, PWM, SWD/JTAG.
A6PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSISPI1MOSI. Supported peripheral buses: UART, SPI, PWM.
A7BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A8PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: UART.
A9VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A10VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B2PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_NSS_I2S3WSJTDI. Supported peripheral buses: UART, SPI, I2C, PWM.
B3PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: CAN.
B4PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: UART, PWM.
B5PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISOI2S3EXTSD, SPI1_MISOUSART2RX. Supported peripheral buses: SPI, PWM, SWD/JTAG.
B6PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: I2C.
B7PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: UART.
B8VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B9PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
B10VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C1PF6Digital_IOSignal terminal PF6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: UART, I2C, PWM.
C2PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
C3PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: CAN.
C4PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: UART, PWM.
C5PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: I2C, PWM.
C6PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDACANTX. Supported peripheral buses: I2C.
C7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C8PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
C9PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: PWM, RTC/CLK.
C10IOC10Digital_IOGeneral Purpose Digital I/O Pin IOC10
D1PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART, CAN.
D2VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D3PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISOI2S3EXTSD. Supported peripheral buses: UART, SPI.
D4PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: UART.
D5PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCLCANRX. Supported peripheral buses: I2C.
D6PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
D7PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
D8VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D9IOD9Digital_IOGeneral Purpose Digital I/O Pin IOD9
D10PF9Digital_IOSignal terminal PF9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF9. Supported peripheral buses: General.
E1PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: I2C, PWM.
E2PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: UART, PWM, CAN.
E3PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: UART.
E4PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCKI2S3CK. Supported peripheral buses: UART, SPI.
E5PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, I2C, PWM.
E6PE8Digital_IOSignal terminal PE8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: PWM.
E7PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: RTC/CLK.
E8PF2Digital_IOSignal terminal PF2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: ADC.
E9NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E10PF10Digital_IOSignal terminal PF10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF10. Supported peripheral buses: General.
F1PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: PWM.
F2PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
F3PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: PWM.
F4PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
F5PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, I2C.
F6PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: UART, ADC.
F7PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC.
F8PE7Digital_IOSignal terminal PE7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
F9PF1 - OSC_OUT (PF1)Digital_IOSignal terminal PF1 - OSC_OUT (PF1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: I2C, RTC/CLK.
F10PF0 - OSC_IN (PF0)Digital_IOSignal terminal PF0 - OSC_IN (PF0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF0 - OSC_IN (PF0). Supported peripheral buses: PWM, RTC/CLK.
G1PD15Digital_IOSignal terminal PD15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_NSSTIM4CH4. Supported peripheral buses: SPI.
G2PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
G3PD13Digital_IOSignal terminal PD13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General.
G4PD9Digital_IOSignal terminal PD9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD9. Supported peripheral buses: UART.
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