ChipDocs.org
⌘K
2284 PARTSUpload PDF
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L431CBY6TR

STID: C2055028WLCSP-49(3.1x3.1) · 49 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L431CBY6TR (WLCSP-49(3.1x3.1))A1VDDA2PA14 (JTCK -A3PB3 (JTDO - A4PB4 (NJTRST)A5PH3/ BOOT0A6PA6A7PA7B1VSSB2PA13 (JTMS -B3PA15 (JTDI)B4PB5B5PB8B6VBATB7PC13C1PA11C2PA10C3PA12C4PB6C5PB9C6IOC6C7PC14 - OSC32D1PA8D2PA9D3PB15D4PB7G7PA1G6PA4G5PB0G4PB1G3PB2G2VSSG1VDDF7VDDA/ VREF+F6PA0F5PA5F4PA6F3PA7F2PB11F1PB12E7VSSA/ VREF -E6PC3E5PA2E4PA3E3PB10E2PB13E1PB14D7PH0 - OSC_ ID6PH1 - OSC_ OD5NRSTGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
G7G6G5G4G3G2G1F7F6F5F4F3F2F1E7E6E5E4E3E2E1D7D6D5D4D3D2D1C7C6C5C4C3C2C1B7B6B5B4B3B2B1A7A6A5A4A3A2A1E=3.10mm · Pitch e=0.40mmD=3.10mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 3.10mm × 3.10mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
A2PA14 (JTCK - SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14 (JTCK - SWCLK) (I2C, SWD/JTAG)
A3PB3 (JTDO - TRACE SWO)I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO - TRACE SWO) (UART, SPI, PWM, SWD/JTAG)
A4PB4 (NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4 (NJTRST) (UART, SPI, I2C, SWD/JTAG)
A5PH3/ BOOT0I/OMultiplexed I/O & Peripheral Pin PH3/ BOOT0 (General)
A6PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
A7PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
B1VSSGNDGround Reference Pin (VSS)
B2PA13 (JTMS - SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13 (JTMS - SWDIO) (SWD/JTAG)
B3PA15 (JTDI)I/OMultiplexed I/O & Peripheral Pin PA15 (JTDI) (UART, SPI, SWD/JTAG)
B4PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C)
B5PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
B6VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B7PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
C1PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, SPI, PWM, CAN)
C2PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, I2C, PWM)
C3PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART, CAN)
C4PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART)
C5PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI)
C6IOC6I/OGeneral Purpose Digital I/O Pin IOC6
C7PC14 - OSC32_I N(PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_I N(PC14) (RTC/CLK)
D1PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, SPI, RTC/CLK)
D2PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, PWM)
D3PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, I2C, PWM, RTC/CLK)
D4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART)
D5NRSTISystem Enable & Hardware Reset (NRST)
D6PH1 - OSC_ OUT (PH1)I/OMultiplexed I/O & Peripheral Pin PH1 - OSC_ OUT (PH1) (RTC/CLK)
D7PH0 - OSC_ IN(PH0)I/OMultiplexed I/O & Peripheral Pin PH0 - OSC_ IN(PH0) (RTC/CLK)
E1PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
E2PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
E3PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, PWM)
E4PA3I/OMultiplexed I/O & Peripheral Pin PA3 (ADC, PWM)
E5PA2I/OMultiplexed I/O & Peripheral Pin PA2 (ADC, PWM)
E6PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI, ADC)
E7VSSA/ VREF -GNDGround Reference Pin (VSSA/ VREF -)
F1PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, I2C)
F2PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, PWM)
F3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
F4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, ADC)
F5PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
F6PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
F7VDDA/ VREF+PowerPower Supply Input (VDDA/ VREF+ — 3.3V VDD (Max 4.0V))
G1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G2VSSGNDGround Reference Pin (VSS)
G3PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C, RTC/CLK)
G4PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
G5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, ADC, PWM)
G6PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
G7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, SPI, ADC, PWM)
PIN A1 VDD
Power
Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 17 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L431CBY6TR (ST · WLCSP-49(3.1x3.1))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) - 4. Package Dimensions (D×E×A)
WLCSP-49(3.1x3.1) · 3.10×3.10mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (17 figures · Page 1/2)
Showing 1–12 of 17 uncropped original figures for STM32L431
P57 · p57_fig02EXACT PACKAGE
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) — Figure 11. STM32L431Cx WLCSP49 pinout(1) 1 2 3 4 5 6 7 VDD PA14 PB3 PB4 PH3/BOOT0 VSS VDD B C D
Figure 11. STM32L431Cx WLCSP49 pinout(1) 1 2 3 4 5 6 7 VDD PA14 PB3 PB4 PH3/BOOT0 VSS VDD B C D
P57 · p57_fig03EXACT PACKAGE
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) — F
F
P58 · p58_fig01EXACT PACKAGE
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) — Figure 12. STM32L431Cx LQFP48 pinout(1)
Figure 12. STM32L431Cx LQFP48 pinout(1)
P58 · p58_fig02EXACT PACKAGE
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) — 10
10
P188 · p188_fig01EXACT PACKAGE
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) — Figure 55. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale
Figure 55. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale
P189 · p189_fig01EXACT PACKAGE
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) — Figure 56. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale
Figure 56. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale
P192 · p192_fig01EXACT PACKAGE
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) — Figure 59. WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale
Figure 59. WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale
P193 · p193_fig01EXACT PACKAGE
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) — Figure 60. WLCSP49 marking (package top view)
Figure 60. WLCSP49 marking (package top view)
P1 · p01_fig01881×407px
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) — • RTC with HW calendar, alarms and calibration
• RTC with HW calendar, alarms and calibration
P57 · p57_fig011546×731px
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) — Figure 9. STM32L431Rx UFBGA64 ballout(1) 1 2 3 4 5 6 7 8 PC14- OSC32_IN PC13 PB9 PB4 PB3 PA15 PA14 PA13 B C D
Figure 9. STM32L431Rx UFBGA64 ballout(1) 1 2 3 4 5 6 7 8 PC14- OSC32_IN PC13 PB9 PB4 PB3 PA15 PA14 PA13 B C D
P57 · p57_fig02P57
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) — Datasheet Page 57 (p57_fig02)
Datasheet Page 57 (p57_fig02)
P85 · p85_fig011546×1275px
STM32L431CBY6TR (WLCSP-49(3.1x3.1)) — Figure 18. Power supply scheme
Figure 18. Power supply scheme
Page 1 / 2 (17 extracted figures)

Technical Specifications & Part Details (STM32L431CBY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L431CBY6TR (WLCSP-49(3.1x3.1)) is a 49-pin embedded microcontroller unit (mcu) featuring a 3.10 × 3.10 × 0.56 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, CAN, PWM, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
80 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
36 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
3.10 × 3.10 × 0.56 mm (A1=0.17 mm)
Package family: WLCSP (WLCSP-49(3.1x3.1))
Pin Count & Lead PitchN / e
49 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, CAN, PWM, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3/ BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-49(3.1x3.1))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.10 × 3.10 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
49P / 49Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-49(3.1x3.1)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L431CBY6TR (WLCSP-49(3.1x3.1))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L431CBY6TR (WLCSP-49(3.1x3.1))?

Manufactured by ST, the STM32L431CBY6TR is housed in a WLCSP-49(3.1x3.1) package with 49 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), A2 (PA14 (JTCK - SWCLK): Multiplexed I/O & Peripheral Pin PA14 (JTCK - SWCLK) (I2C, SWD/JTAG)), A3 (PB3 (JTDO - TRACE SWO): Multiplexed I/O & Peripheral Pin PB3 (JTDO - TRACE SWO) (UART, SPI, PWM, SWD/JTAG)), A4 (PB4 (NJTRST): Multiplexed I/O & Peripheral Pin PB4 (NJTRST) (UART, SPI, I2C, SWD/JTAG)), A5 (PH3/ BOOT0: Multiplexed I/O & Peripheral Pin PH3/ BOOT0 (General)), A6 (PA6: Multiplexed I/O & Peripheral Pin PA6 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32L431CBY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L431CBY6TR (WLCSP-49(3.1x3.1)) has a nominal body envelope of 3.10 × 3.10 mm, pitch e = 0.40 mm, and 49 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L431CBY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L431CBY6TR (ST, WLCSP-49(3.1x3.1)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & STM32L431 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A2PA14 (JTCK - SWCLK)Digital_IOSignal terminal PA14 (JTCK - SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA. Supported peripheral buses: I2C, SWD/JTAG.
A3PB3 (JTDO - TRACE SWO)Digital_IOSignal terminal PB3 (JTDO - TRACE SWO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI, PWM, SWD/JTAG.
A4PB4 (NJTRST)Digital_IOSignal terminal PB4 (NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA, SPI1_MISOSPI3MISO. Supported peripheral buses: UART, SPI, I2C, SWD/JTAG.
A5PH3/ BOOT0Digital_IOSignal terminal PH3/ BOOT0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH3/ BOOT0. Supported peripheral buses: General.
A6PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
A7PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
B1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B2PA13 (JTMS - SWDIO)Digital_IOSignal terminal PA13 (JTMS - SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMS - SWDIO). Supported peripheral buses: SWD/JTAG.
B3PA15 (JTDI)Digital_IOSignal terminal PA15 (JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSSSPI3NSS. Supported peripheral buses: UART, SPI, SWD/JTAG.
B4PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSISPI3MOSI. Supported peripheral buses: UART, SPI, I2C.
B5PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: I2C.
B6VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B7PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
C1PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, PWM, CAN.
C2PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART, I2C, PWM.
C3PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART, CAN.
C4PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART.
C5PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSCAN1TX. Supported peripheral buses: SPI.
C6IOC6Digital_IOGeneral Purpose Digital I/O Pin IOC6
C7PC14 - OSC32_I N(PC14)Digital_IOSignal terminal PC14 - OSC32_I N(PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_I N(PC14). Supported peripheral buses: RTC/CLK.
D1PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, SPI, RTC/CLK.
D2PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, PWM.
D3PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, I2C, PWM, RTC/CLK.
D4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART.
D5NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
D6PH1 - OSC_ OUT (PH1)Digital_IOSignal terminal PH1 - OSC_ OUT (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC_ OUT (PH1). Supported peripheral buses: RTC/CLK.
D7PH0 - OSC_ IN(PH0)Digital_IOSignal terminal PH0 - OSC_ IN(PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC_ IN(PH0). Supported peripheral buses: RTC/CLK.
E1PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, PWM.
E2PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
E3PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKUSART3TX. Supported peripheral buses: SPI, PWM.
E4PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: ADC, PWM.
E5PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: ADC, PWM.
E6PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI_SAI1SDA. Supported peripheral buses: SPI, ADC.
E7VSSA/ VREF -GND0V electrical ground return terminal (VSSA/ VREF -) for internal core logic, I/O drivers, and analog sub-blocks.
F1PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: UART, I2C.
F2PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: UART, PWM.
F3PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
F4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: UART, ADC.
F5PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC, PWM.
F6PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
F7VDDA/ VREF+Power_InPrimary positive power supply input (VDDA/ VREF+) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
G1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
G2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
G3PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SMBAEVENTOUT. Supported peripheral buses: I2C, RTC/CLK.
G4PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM.
G5PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: UART, ADC, PWM.
G6PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSSPI3NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
G7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, ADC, PWM.
ExplorePartsPackagesMFRsUpload