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STM32L433CBY6TR (WLCSP-49(3.1x3.1)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L433CBY6TR

STWLCSP-49(3.1x3.1) · 49 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L433CBY6TR (WLCSP-49(3.1x3.1))A1PA1A2PA2A3PA3A4PA4A5PA5A6PA6A7PA7B1PB1B2PB2B3PB3B4PB4B5PB5B6VBATB7PC13C1PC1C2PC2C3PC3C4PC4C5PC5C6IOC6C7PC14 - OSC32D1PD1D2PD2D3PD3D4PD4G7PA1G6PA4G5PB0G4PB1G3PB2G2PG2G1PG1F7VDDA/ VREF+F6PA0F5PA5F4PA6F3PA7F2PF2F1PF1E7VSSA/ VREF -E6PC3E5PA2E4PA3E3PE3E2PE2E1PE1D7PH0 - OSC_ ID6PH1 - OSC_ OD5NRSTGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1A2B2C2D2E2F2G2A3B3C3D3E3F3G3A4B4C4D4E4F4G4A5B5C5D5E5F5G5A6B6C6D6E6F6G6A7B7C7D7E7F7G7E=3.10mm · Pitch e=0.40mmD=3.10mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 3.10mm × 3.10mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
A2PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
A3PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
A4PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
A5PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
A6PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
A7PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
B1PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
B2PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
B3PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
B4PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
B5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
B6VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B7PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
C1PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
C2PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
C3PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
C4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
C5PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
C6IOC6I/OGeneral Purpose Digital I/O Pin IOC6
C7PC14 - OSC32_ IN(PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_ IN(PC14) (RTC/CLK)
D1PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
D2PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
D3PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
D4PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
D5NRSTISystem Enable & Hardware Reset (NRST)
D6PH1 - OSC_ OUT (PH1)I/OMultiplexed I/O & Peripheral Pin PH1 - OSC_ OUT (PH1) (RTC/CLK)
D7PH0 - OSC_ IN(PH0)I/OMultiplexed I/O & Peripheral Pin PH0 - OSC_ IN(PH0) (RTC/CLK)
E1PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
E2PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
E3PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
E4PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
E5PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
E6PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI, I2C, ADC)
E7VSSA/ VREF -GNDGround Reference Pin (VSSA/ VREF -)
F1PF1I/OMultiplexed I/O & Peripheral Pin PF1 (General)
F2PF2I/OMultiplexed I/O & Peripheral Pin PF2 (General)
F3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, I2C, ADC, PWM)
F4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC)
F5PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
F6PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
F7VDDA/ VREF+PowerPower Supply Input (VDDA/ VREF+ — 3.3V VDD (Max 4.0V))
G1PG1I/OMultiplexed I/O & Peripheral Pin PG1 (General)
G2PG2I/OMultiplexed I/O & Peripheral Pin PG2 (General)
G3PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C, RTC/CLK)
G4PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
G5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC, PWM)
G6PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
G7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, SPI, I2C, ADC, PWM)
PIN A1 PA1
I/O
Multiplexed I/O & Peripheral Pin PA1 (General)
Design note: Signal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L433CBY6TR (ST · WLCSP-49(3.1x3.1))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) - 4. Package Dimensions (D×E×A)
WLCSP-49(3.1x3.1) · 3.10×3.10mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for STM32L433
P59 · p59_fig01EXACT PACKAGE
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) — Figure 11. STM32L433Rx WLCSP64 pinout(1) 1 2 3 4 5 6 7 8 VDDUSB PA15 PC12 PD2 PB3 PB7 VSS VDD B C D
Figure 11. STM32L433Rx WLCSP64 pinout(1) 1 2 3 4 5 6 7 8 VDDUSB PA15 PC12 PD2 PB3 PB7 VSS VDD B C D
P59 · p59_fig02EXACT PACKAGE
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) — F
F
P60 · p60_fig01EXACT PACKAGE
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) — Figure 13. STM32L433Cx LQFP48 pinout(1)
Figure 13. STM32L433Cx LQFP48 pinout(1)
P60 · p60_fig02EXACT PACKAGE
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) — 10
10
P207 · p207_fig01EXACT PACKAGE
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) — Figure 55. WLCSP64 - Outline
Figure 55. WLCSP64 - Outline
P208 · p208_fig01EXACT PACKAGE
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) — Figure 56. WLCSP64 - Recommended footprint
Figure 56. WLCSP64 - Recommended footprint
P210 · p210_fig01EXACT PACKAGE
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) — Figure 58. WLCSP49 - Outline
Figure 58. WLCSP49 - Outline
P211 · p211_fig01EXACT PACKAGE
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) — Figure 59. WLCSP49 - Recommended footprint
Figure 59. WLCSP49 - Recommended footprint
P212 · p212_fig01EXACT PACKAGE
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) — Figure 60. WLCSP49 marking (package top view)
Figure 60. WLCSP49 marking (package top view)
P1 · p01_fig01881×524px
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) — Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,
Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,
P91 · p91_fig011546×1275px
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) — Figure 18. Power supply scheme
Figure 18. Power supply scheme
P133 · p133_fig011546×702px
STM32L433CBY6TR (WLCSP-49(3.1x3.1)) — Figure 23. Typical application with an 8 MHz crystal
Figure 23. Typical application with an 8 MHz crystal
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (STM32L433CBY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L433CBY6TR (WLCSP-49(3.1x3.1)) is a 49-pin embedded microcontroller unit (mcu) featuring a 3.10 × 3.10 × 0.56 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
80 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
14 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
3.10 × 3.10 × 0.56 mm (A1=0.17 mm)
Package family: WLCSP (WLCSP-49(3.1x3.1))
Pin Count & Lead PitchN / e
49 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-49(3.1x3.1))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.10 × 3.10 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
49P / 49Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-49(3.1x3.1)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L433CBY6TR (WLCSP-49(3.1x3.1))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L433CBY6TR (WLCSP-49(3.1x3.1))?

Manufactured by ST, the STM32L433CBY6TR is housed in a WLCSP-49(3.1x3.1) package with 49 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (PA1: Multiplexed I/O & Peripheral Pin PA1 (General)), A2 (PA2: Multiplexed I/O & Peripheral Pin PA2 (General)), A3 (PA3: Multiplexed I/O & Peripheral Pin PA3 (General)), A4 (PA4: Multiplexed I/O & Peripheral Pin PA4 (General)), A5 (PA5: Multiplexed I/O & Peripheral Pin PA5 (General)), A6 (PA6: Multiplexed I/O & Peripheral Pin PA6 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32L433CBY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L433CBY6TR (WLCSP-49(3.1x3.1)) has a nominal body envelope of 3.10 × 3.10 mm, pitch e = 0.40 mm, and 49 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L433CBY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L433CBY6TR (ST, WLCSP-49(3.1x3.1)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & STM32L433 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
A2PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
A3PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
A4PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
A5PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
A6PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
A7PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
B1PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
B2PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
B3PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
B4PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
B5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
B6VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B7PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
C1PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
C2PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
C3PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
C4PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
C5PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
C6IOC6Digital_IOGeneral Purpose Digital I/O Pin IOC6
C7PC14 - OSC32_ IN(PC14)Digital_IOSignal terminal PC14 - OSC32_ IN(PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_ IN(PC14). Supported peripheral buses: RTC/CLK.
D1PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
D2PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
D3PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
D4PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
D5NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
D6PH1 - OSC_ OUT (PH1)Digital_IOSignal terminal PH1 - OSC_ OUT (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC_ OUT (PH1). Supported peripheral buses: RTC/CLK.
D7PH0 - OSC_ IN(PH0)Digital_IOSignal terminal PH0 - OSC_ IN(PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC_ IN(PH0). Supported peripheral buses: RTC/CLK.
E1PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
E2PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
E3PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
E4PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
E5PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
E6PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, I2C, ADC.
E7VSSA/ VREF -GND0V electrical ground return terminal (VSSA/ VREF -) for internal core logic, I/O drivers, and analog sub-blocks.
F1PF1Digital_IOSignal terminal PF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General.
F2PF2Digital_IOSignal terminal PF2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General.
F3PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL, SPI1_MOSI. Supported peripheral buses: SPI, I2C, ADC, PWM.
F4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC.
F5PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC, PWM.
F6PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
F7VDDA/ VREF+Power_InPrimary positive power supply input (VDDA/ VREF+) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
G1PG1Digital_IOSignal terminal PG1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG1. Supported peripheral buses: General.
G2PG2Digital_IOSignal terminal PG2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG2. Supported peripheral buses: General.
G3PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SMBA. Supported peripheral buses: I2C, RTC/CLK.
G4PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM.
G5PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, PWM.
G6PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
G7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_SCK. Supported peripheral buses: UART, SPI, I2C, ADC, PWM.
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