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STM32L422TBY6TR (WLCSP-36(2.6x3.1)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L422TBY6TR

STID: C2054783WLCSP-36(2.6x3.1) · 36 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L422TBY6TR (WLCSP-36(2.6x3.1))A1PA12A2PA14 (JTCK/SA3PB4(NJTRST)A4PB7A5VSSA6VDDB1PA11B2PA13 (JTMS/SB3PB3 (JTDO/TRB4PB6B5PB8B6PC14OSC32 INC1PA9C2PA10C3PA15(JTDI)C4PB5C5PH3BOOT0 - (C6IOC6F6VDDAF5PA3F4PA4F3PB0F2PB10F1VSSE6VREF+E5PA2E4PA5E3PA7E2PB2E1VDDD6NRSTD5PA0 CK IN -_D4PA1D3PA6D2PB1D1PA8Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
A1B1C1D1E1F1A2B2C2D2E2F2A3B3C3D3E3F3A4B4C4D4E4F4A5B5C5D5E5F5A6B6C6D6E6F6E=2.60mm · Pitch e=0.40mmD=3.10mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.60mm × 3.10mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (36/36)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART)
A2PA14 (JTCK/SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14 (JTCK/SWCLK) (I2C, SWD/JTAG)
A3PB4(NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4(NJTRST) (UART, SPI, I2C, SWD/JTAG)
A4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
A5VSSGNDGround Reference Pin (VSS)
A6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
B1PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB)
B2PA13 (JTMS/SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13 (JTMS/SWDIO) (USB, SWD/JTAG)
B3PB3 (JTDO/TRACES WO)I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO/TRACES WO) (UART, SPI, SWD/JTAG)
B4PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
B5PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
B6PC14OSC32 IN -_ (PC14)I/OMultiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (PC14) (RTC/CLK)
C1PA9I/OMultiplexed I/O & Peripheral Pin PA9 (I2C)
C2PA10I/OMultiplexed I/O & Peripheral Pin PA10 (USB, I2C)
C3PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SWD/JTAG)
C4PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C)
C5PH3BOOT0 - (BOOT0)I/OMultiplexed I/O & Peripheral Pin PH3BOOT0 - (BOOT0) (General)
C6IOC6I/OGeneral Purpose Digital I/O Pin IOC6
D1PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
D2PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART)
D3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, ADC)
D4PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, I2C)
D5PA0 CK IN -_I/OMultiplexed I/O & Peripheral Pin PA0 CK IN -_ (PWM, RTC/CLK)
D6NRSTISystem Enable & Hardware Reset (NRST)
E1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E2PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
E3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (I2C, ADC)
E4PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
E5PA2I/OMultiplexed I/O & Peripheral Pin PA2 (ADC, PWM)
E6VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
F1VSSGNDGround Reference Pin (VSS)
F2PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, I2C)
F3PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC)
F4PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI)
F5PA3I/OMultiplexed I/O & Peripheral Pin PA3 (ADC, PWM)
F6VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
PIN A1 PA12
I/O
Multiplexed I/O & Peripheral Pin PA12 (UART)
Design note: Alt: TIM1_ETRSPI1MOSI ,_ , USART1 RTS_DEUSBDP_ ,_ , EVENTOUT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L422TBY6TR (ST · WLCSP-36(2.6x3.1))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) - 2. Standard Pinout (Top View)
True package pinout (36 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) - 4. Package Dimensions (D×E×A)
WLCSP-36(2.6x3.1) · 2.60×3.10mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) - 5. Recommended Land Pattern
IPC-7351B Footprint (36 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for STM32L422
P53 · p53_fig01EXACT PACKAGE
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) — Figure 9. STM32L422Tx WLCSP36 ballout(1)
Figure 9. STM32L422Tx WLCSP36 ballout(1)
P171 · p171_fig01EXACT PACKAGE
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) — Figure 48. WLCSP - 36 balls, 2.58 x 3.07 mm, 0.4 mm pitch, wafer level chip scale
Figure 48. WLCSP - 36 balls, 2.58 x 3.07 mm, 0.4 mm pitch, wafer level chip scale
P53 · p53_fig01P53
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) — Datasheet Page 53 (p53_fig01)
Datasheet Page 53 (p53_fig01)
P72 · p72_fig011546×1275px
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) — Figure 15. Power supply scheme
Figure 15. Power supply scheme
P72 · p72_fig01P72
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) — Datasheet Page 72 (p72_fig01)
Datasheet Page 72 (p72_fig01)
P108 · p108_fig011546×702px
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) — Figure 20. Typical application with an 8 MHz crystal
Figure 20. Typical application with an 8 MHz crystal
P109 · p109_fig011546×702px
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) — Figure 21. Typical application with a 32.768 kHz crystal
Figure 21. Typical application with a 32.768 kHz crystal
P141 · p141_fig011546×641px
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) — Figure 29. Typical connection diagram using the ADC
Figure 29. Typical connection diagram using the ADC
P160 · p160_fig011546×1477px
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) — Figure 39. UFBGA64 - 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid
Figure 39. UFBGA64 - 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid
P171 · p171_fig01P171
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) — Datasheet Page 171 (p171_fig01)
Datasheet Page 171 (p171_fig01)
P1 · p01_fig01All Packages in PDF
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) — • RTC with HW calendar, alarms and calibration
• RTC with HW calendar, alarms and calibration
P53 · p53_fig02All Packages in PDF
STM32L422TBY6TR (WLCSP-36(2.6x3.1)) — Figure 10. STM32L422Kx LQFP32 pinout(1)
Figure 10. STM32L422Kx LQFP32 pinout(1)

Technical Specifications & Part Details (STM32L422TBY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L422TBY6TR (WLCSP-36(2.6x3.1)) is a 36-pin embedded microcontroller unit (mcu) featuring a 3.10 × 2.60 × 0.56 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
80 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
26 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
3.10 × 2.60 × 0.56 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-36(2.6x3.1))
Pin Count & Lead PitchN / e
36 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3BOOT0 - (BOOT0)): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol36 auto-grouped pins
OK
IPC-7351B Land Pattern36 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-36(2.6x3.1))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.10 × 2.60 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
36P / 36Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-36(2.6x3.1)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L422TBY6TR (WLCSP-36(2.6x3.1))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L422TBY6TR (WLCSP-36(2.6x3.1))?

Manufactured by ST, the STM32L422TBY6TR is housed in a WLCSP-36(2.6x3.1) package with 36 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (PA12: Multiplexed I/O & Peripheral Pin PA12 (UART)), A2 (PA14 (JTCK/SWCLK): Multiplexed I/O & Peripheral Pin PA14 (JTCK/SWCLK) (I2C, SWD/JTAG)), A3 (PB4(NJTRST): Multiplexed I/O & Peripheral Pin PB4(NJTRST) (UART, SPI, I2C, SWD/JTAG)), A4 (PB7: Multiplexed I/O & Peripheral Pin PB7 (UART, I2C)), A5 (VSS: Ground Reference Pin (VSS)), A6 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))).

What are the IPC-7351B PCB Footprint dimensions for STM32L422TBY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L422TBY6TR (WLCSP-36(2.6x3.1)) has a nominal body envelope of 2.60 × 3.10 mm, pitch e = 0.40 mm, and 36 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L422TBY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L422TBY6TR (ST, WLCSP-36(2.6x3.1)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (36 pins) & STM32L422 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART.
A2PA14 (JTCK/SWCLK)Digital_IOSignal terminal PA14 (JTCK/SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBAEVENTOUT. Supported peripheral buses: I2C, SWD/JTAG.
A3PB4(NJTRST)Digital_IOSignal terminal PB4(NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA, SPI1_MISO. Supported peripheral buses: UART, SPI, I2C, SWD/JTAG.
A4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
A5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
A6VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B1PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: USB.
B2PA13 (JTMS/SWDIO)Digital_IOSignal terminal PA13 (JTMS/SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMS/SWDIO). Supported peripheral buses: USB, SWD/JTAG.
B3PB3 (JTDO/TRACES WO)Digital_IOSignal terminal PB3 (JTDO/TRACES WO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK_USART1RTSDE. Supported peripheral buses: UART, SPI, SWD/JTAG.
B4PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C.
B5PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: I2C.
B6PC14OSC32 IN -_ (PC14)Digital_IOSignal terminal PC14OSC32 IN -_ (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14OSC32 IN -_ (PC14). Supported peripheral buses: RTC/CLK.
C1PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: I2C.
C2PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: USB, I2C.
C3PA15(JTDI)Digital_IOSignal terminal PA15(JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA15(JTDI). Supported peripheral buses: UART, SWD/JTAG.
C4PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSIUSART1CK. Supported peripheral buses: SPI, I2C.
C5PH3BOOT0 - (BOOT0)Digital_IOSignal terminal PH3BOOT0 - (BOOT0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH3BOOT0 - (BOOT0). Supported peripheral buses: General.
C6IOC6Digital_IOGeneral Purpose Digital I/O Pin IOC6
D1PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
D2PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART.
D3PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: UART, ADC.
D4PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, I2C.
D5PA0 CK IN -_Digital_IOSignal terminal PA0 CK IN -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0 CK IN -_. Supported peripheral buses: PWM, RTC/CLK.
D6NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E2PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
E3PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: I2C, ADC.
E4PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
E5PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: ADC, PWM.
E6VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
F1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F2PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB10. Supported peripheral buses: UART, I2C.
F3PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC.
F4PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSUSART2CK. Supported peripheral buses: SPI.
F5PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: ADC, PWM.
F6VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
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