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STM32L071CBT6TR (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L071CBT6TR

STID: C2053942LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L071CBT6TR (LQFP-48(7x7))1VDD2PC133PC14 - OSC324NC5PH0OSC IN -_6PH1 - OSC_OU7NRST8VSSA9VDDA10PA011PA112PA213PA314PA415PA516PA617PA718PB019PB120PB221PB1022PB1123VSS24VDD48VDD47VSS46PB945PB844BOOT043PB742PB641PB540PB439PB338PA1537PA1436VDDIO235VSS34PA1333PA1232PA1131PA1030PA929PA828PB1527PB1426PB1325PB12Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.835.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
3PC14 - OSC32_IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)
4NCNCNo Connect (Leave Floating)
5PH0OSC IN -_ (PH0)I/OMultiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (RTC/CLK)
6PH1 - OSC_OUT (PH1)I/OMultiplexed I/O & Peripheral Pin PH1 - OSC_OUT (PH1) (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8VSSAGNDGround Reference Pin (VSSA)
9VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
10PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
11PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
12PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
13PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
14PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
15PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
16PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC, PWM)
17PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
18PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
19PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
20PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C)
21PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, I2C, PWM)
22PB11I/OMultiplexed I/O & Peripheral Pin PB11 (I2C, PWM)
23VSSGNDGround Reference Pin (VSS)
24VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
25PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
26PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, I2C, RTC/CLK)
27PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, I2C, RTC/CLK)
28PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, RTC/CLK)
29PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, I2C, RTC/CLK)
30PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C, RTC/CLK)
31PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, I2C)
32PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, SPI)
33PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART, SPI)
34PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
35VSSGNDGround Reference Pin (VSS)
36VDDIO2PowerPower Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))
37PA14I/OMultiplexed I/O & Peripheral Pin PA14 (UART, SWD/JTAG)
38PA15I/OMultiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)
39PB3I/OMultiplexed I/O & Peripheral Pin PB3 (UART, SPI, PWM)
40PB4I/OMultiplexed I/O & Peripheral Pin PB4 (UART, SPI, I2C, PWM)
41PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C)
42PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
43PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
44BOOT0IInput-Only Pin BOOT0 (General)
45PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
46PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI, I2C)
47VSSGNDGround Reference Pin (VSS)
48VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
PIN 1 VDD
Power
Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L071CBT6TR (ST · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L071CBT6TR (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L071CBT6TR (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L071CBT6TR (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L071CBT6TR (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L071CBT6TR (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L071CBT6TR (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for STM32L071
P1 · p01_fig01EXACT PACKAGE
STM32L071CBT6TR (LQFP-48(7x7)) — STM32L071xZ Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0+,
STM32L071xZ Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0+,
P38 · p38_fig01EXACT PACKAGE
STM32L071CBT6TR (LQFP-48(7x7)) — Figure 8. STM32L071xx LQFP48 pinout
Figure 8. STM32L071xx LQFP48 pinout
P129 · p129_fig01EXACT PACKAGE
STM32L071CBT6TR (LQFP-48(7x7)) — Figure 55. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline
Figure 55. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline
P130 · p130_fig01EXACT PACKAGE
STM32L071CBT6TR (LQFP-48(7x7)) — Figure 56. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint
Figure 56. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint
P38 · p38_fig021546×994px
STM32L071CBT6TR (LQFP-48(7x7)) — Figure 9. STM32L071xx UFQFPN48
Figure 9. STM32L071xx UFQFPN48
P38 · p38_fig01P38
STM32L071CBT6TR (LQFP-48(7x7)) — Datasheet Page 38 (p38_fig01)
Datasheet Page 38 (p38_fig01)
P57 · p57_fig011751×1436px
STM32L071CBT6TR (LQFP-48(7x7)) — Figure 14. Power supply scheme
Figure 14. Power supply scheme
P57 · p57_fig021546×555px
STM32L071CBT6TR (LQFP-48(7x7)) — Figure 15. Current consumption measurement scheme
Figure 15. Current consumption measurement scheme
P57 · p57_fig01P57
STM32L071CBT6TR (LQFP-48(7x7)) — Datasheet Page 57 (p57_fig01)
Datasheet Page 57 (p57_fig01)
P101 · p101_fig011546×705px
STM32L071CBT6TR (LQFP-48(7x7)) — Figure 31. Typical connection diagram using the ADC
Figure 31. Typical connection diagram using the ADC
P101 · p101_fig021546×975px
STM32L071CBT6TR (LQFP-48(7x7)) — Figure 32. Power supply and reference decoupling (VREF+ not connected to VDDA)
Figure 32. Power supply and reference decoupling (VREF+ not connected to VDDA)
P129 · p129_fig01P129
STM32L071CBT6TR (LQFP-48(7x7)) — Datasheet Page 129 (p129_fig01)
Datasheet Page 129 (p129_fig01)
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (STM32L071CBT6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L071CBT6TR (LQFP-48(7x7)) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.65 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, I2S, ADC, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.65 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
31 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.20 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L071CBT6TR (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L071CBT6TR (LQFP-48(7x7))?

Manufactured by ST, the STM32L071CBT6TR is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.65 V to 3.6 V. Key pins include: 1 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (PC14 - OSC32_IN (PC14): Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)), 4 (NC: No Connect (Leave Floating)), 5 (PH0OSC IN -_ (PH0): Multiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (RTC/CLK)), 6 (PH1 - OSC_OUT (PH1): Multiplexed I/O & Peripheral Pin PH1 - OSC_OUT (PH1) (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32L071CBT6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L071CBT6TR (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L071CBT6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L071CBT6TR (ST, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & STM32L071 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
3PC14 - OSC32_IN (PC14)Digital_IOSignal terminal PC14 - OSC32_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN (PC14). Supported peripheral buses: RTC/CLK.
4NCNo_ConnectNo Connect (Leave Floating)
5PH0OSC IN -_ (PH0)Digital_IOSignal terminal PH0OSC IN -_ (PH0) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0OSC IN -_ (PH0). Supported peripheral buses: RTC/CLK.
6PH1 - OSC_OUT (PH1)Digital_IOSignal terminal PH1 - OSC_OUT (PH1) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1 - OSC_OUT (PH1). Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
9VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
10PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
11PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
12PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
13PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
14PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC.
15PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, PWM.
16PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC, PWM.
17PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
18PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
19PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM.
20PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SMBA. Supported peripheral buses: I2C.
21PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK, I2C2_SCL. Supported peripheral buses: SPI, I2C, PWM.
22PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: I2C, PWM.
23VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
24VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
25PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, I2C2_SMBA. Supported peripheral buses: UART, SPI, I2C.
26PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK, I2C2_SCL. Supported peripheral buses: UART, SPI, I2C, RTC/CLK.
27PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO, I2C2_SDA. Supported peripheral buses: UART, SPI, I2C, RTC/CLK.
28PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, RTC/CLK.
29PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL. Supported peripheral buses: UART, I2C, RTC/CLK.
30PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL, I2C3_SMBA. Supported peripheral buses: UART, I2C, RTC/CLK.
31PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
32PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI.
33PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI.
34PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
35VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
36VDDIO2Power_InPrimary positive power supply input (VDDIO2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
37PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: UART, SWD/JTAG.
38PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, PWM.
39PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, PWM.
40PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, I2C3_SDA. Supported peripheral buses: UART, SPI, I2C, PWM.
41PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, I2C1_SMBA. Supported peripheral buses: UART, SPI, I2C.
42PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C.
43PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
44BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
45PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
46PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA, SPI2_NSS. Supported peripheral buses: SPI, I2C.
47VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
48VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
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