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STM32L071CZY6TR (WLCSP-49(3.3x3.3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L071CZY6TR

STID: C2053665WLCSP-49(3.3x3.3) · 49 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L071CZY6TR (WLCSP-49(3.3x3.3))A1VDDIO2A2PA15A3PB3A4PB5A5BOOT0A6PB9A7VDDB1PA12B2PA14B3PB4B4PB6B5PB8B6VDDB7PC13C1PA10C2PA13C3PB7C4PC1C5PC0C6PC14 - OSC32C7IOC7D1PA8D2PA11D3PB1D4VSSG7PA3G6PA5G5PA6G4PB0G3PB10G2VDDG1PB12F7VDDAF6PA2F5PA4F4PA7F3PB11F2PB13F1PB14E7PC2E6VREF+E5PA0E4PA1E3PB2E2PA9E1PB15D7PH1 - OSC_OUD6PH0OSC IN -_D5NRSTGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1A2B2C2D2E2F2G2A3B3C3D3E3F3G3A4B4C4D4E4F4G4A5B5C5D5E5F5G5A6B6C6D6E6F6G6A7B7C7D7E7F7G7E=3.30mm · Pitch e=0.40mmD=3.30mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 3.30mm × 3.30mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VDDIO2PowerPower Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))
A2PA15I/OMultiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)
A3PB3I/OMultiplexed I/O & Peripheral Pin PB3 (UART, SPI, PWM)
A4PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C)
A5BOOT0IInput-Only Pin BOOT0 (General)
A6PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI, I2C)
A7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
B1PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART, SPI)
B2PA14I/OMultiplexed I/O & Peripheral Pin PA14 (UART, SWD/JTAG)
B3PB4I/OMultiplexed I/O & Peripheral Pin PB4 (UART, SPI, I2C, PWM)
B4PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
B5PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
B6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
B7PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
C1PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, I2C)
C2PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
C3PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
C4PC1I/OMultiplexed I/O & Peripheral Pin PC1 (I2C, ADC)
C5PC0I/OMultiplexed I/O & Peripheral Pin PC0 (I2C, ADC)
C6PC14 - OSC32_IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)
C7IOC7I/OGeneral Purpose Digital I/O Pin IOC7
D1PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, I2C, RTC/CLK)
D2PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, SPI)
D3PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
D4VSSGNDGround Reference Pin (VSS)
D5NRSTISystem Enable & Hardware Reset (NRST)
D6PH0OSC IN -_ (PH0)I/OMultiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (RTC/CLK)
D7PH1 - OSC_OUT (PH1)I/OMultiplexed I/O & Peripheral Pin PH1 - OSC_OUT (PH1) (RTC/CLK)
E1PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, RTC/CLK)
E2PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C, RTC/CLK)
E3PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C)
E4PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
E5PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
E6VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
E7PC2I/OMultiplexed I/O & Peripheral Pin PC2 (SPI, ADC)
F1PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, I2C, RTC/CLK)
F2PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, I2C, RTC/CLK)
F3PB11I/OMultiplexed I/O & Peripheral Pin PB11 (I2C, PWM)
F4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
F5PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
F6PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
F7VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
G1PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
G2VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G3PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, I2C, PWM)
G4PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
G5PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC, PWM)
G6PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
G7PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
PIN A1 VDDIO2
Power
Power Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VDDIO2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L071CZY6TR (ST · WLCSP-49(3.3x3.3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) - 4. Package Dimensions (D×E×A)
WLCSP-49(3.3x3.3) · 3.30×3.30mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for STM32L071
P1 · p01_fig01EXACT PACKAGE
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) — STM32L071xZ Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0+,
STM32L071xZ Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0+,
P37 · p37_fig01EXACT PACKAGE
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) — Figure 7. STM32L071xx WLCSP49 ballout 1 2 3 4 5 6 VDD IO2
Figure 7. STM32L071xx WLCSP49 ballout 1 2 3 4 5 6 VDD IO2
P126 · p126_fig01EXACT PACKAGE
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) — Figure 52. WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale
Figure 52. WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale
P127 · p127_fig01EXACT PACKAGE
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) — Figure 53. WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale
Figure 53. WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale
P128 · p128_fig01EXACT PACKAGE
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) — Figure 54. WLCSP49 marking example (package top view)
Figure 54. WLCSP49 marking example (package top view)
P34 · p34_fig011546×1379px
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) — Figure 3. STM32L071xx LQFP100 pinout
Figure 3. STM32L071xx LQFP100 pinout
P34 · p34_fig01P34
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) — Datasheet Page 34 (p34_fig01)
Datasheet Page 34 (p34_fig01)
P57 · p57_fig011751×1436px
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) — Figure 14. Power supply scheme
Figure 14. Power supply scheme
P57 · p57_fig021546×555px
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) — Figure 15. Current consumption measurement scheme
Figure 15. Current consumption measurement scheme
P57 · p57_fig01P57
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) — Datasheet Page 57 (p57_fig01)
Datasheet Page 57 (p57_fig01)
P101 · p101_fig011546×705px
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) — Figure 31. Typical connection diagram using the ADC
Figure 31. Typical connection diagram using the ADC
P101 · p101_fig021546×975px
STM32L071CZY6TR (WLCSP-49(3.3x3.3)) — Figure 32. Power supply and reference decoupling (VREF+ not connected to VDDA)
Figure 32. Power supply and reference decoupling (VREF+ not connected to VDDA)
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (STM32L071CZY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L071CZY6TR (WLCSP-49(3.3x3.3)) is a 49-pin embedded microcontroller unit (mcu) featuring a 3.30 × 3.30 × 0.56 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.65 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, I2S, ADC, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.65 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
34 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
3.30 × 3.30 × 0.56 mm (A1=0.17 mm)
Package family: WLCSP (WLCSP-49(3.3x3.3))
Pin Count & Lead PitchN / e
49 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-49(3.3x3.3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.30 × 3.30 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.21 × 0.21 mm
Pins / Total PadsTopology
49P / 49Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-49(3.3x3.3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L071CZY6TR (WLCSP-49(3.3x3.3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L071CZY6TR (WLCSP-49(3.3x3.3))?

Manufactured by ST, the STM32L071CZY6TR is housed in a WLCSP-49(3.3x3.3) package with 49 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.65 V to 3.6 V. Key pins include: A1 (VDDIO2: Power Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))), A2 (PA15: Multiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)), A3 (PB3: Multiplexed I/O & Peripheral Pin PB3 (UART, SPI, PWM)), A4 (PB5: Multiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C)), A5 (BOOT0: Input-Only Pin BOOT0 (General)), A6 (PB9: Multiplexed I/O & Peripheral Pin PB9 (SPI, I2C)).

What are the IPC-7351B PCB Footprint dimensions for STM32L071CZY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L071CZY6TR (WLCSP-49(3.3x3.3)) has a nominal body envelope of 3.30 × 3.30 mm, pitch e = 0.40 mm, and 49 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L071CZY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L071CZY6TR (ST, WLCSP-49(3.3x3.3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & STM32L071 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VDDIO2Power_InPrimary positive power supply input (VDDIO2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A2PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, PWM.
A3PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, PWM.
A4PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, I2C1_SMBA. Supported peripheral buses: UART, SPI, I2C.
A5BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A6PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA, SPI2_NSS. Supported peripheral buses: SPI, I2C.
A7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B1PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI.
B2PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: UART, SWD/JTAG.
B3PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, I2C3_SDA. Supported peripheral buses: UART, SPI, I2C, PWM.
B4PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C.
B5PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
B6VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B7PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
C1PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
C2PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
C3PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
C4PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA. Supported peripheral buses: I2C, ADC.
C5PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL. Supported peripheral buses: I2C, ADC.
C6PC14 - OSC32_IN (PC14)Digital_IOSignal terminal PC14 - OSC32_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN (PC14). Supported peripheral buses: RTC/CLK.
C7IOC7Digital_IOGeneral Purpose Digital I/O Pin IOC7
D1PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL. Supported peripheral buses: UART, I2C, RTC/CLK.
D2PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI.
D3PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM.
D4VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D5NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
D6PH0OSC IN -_ (PH0)Digital_IOSignal terminal PH0OSC IN -_ (PH0) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0OSC IN -_ (PH0). Supported peripheral buses: RTC/CLK.
D7PH1 - OSC_OUT (PH1)Digital_IOSignal terminal PH1 - OSC_OUT (PH1) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1 - OSC_OUT (PH1). Supported peripheral buses: RTC/CLK.
E1PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, RTC/CLK.
E2PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL, I2C3_SMBA. Supported peripheral buses: UART, I2C, RTC/CLK.
E3PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SMBA. Supported peripheral buses: I2C.
E4PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
E5PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
E6VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
E7PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, ADC.
F1PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO, I2C2_SDA. Supported peripheral buses: UART, SPI, I2C, RTC/CLK.
F2PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK, I2C2_SCL. Supported peripheral buses: UART, SPI, I2C, RTC/CLK.
F3PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: I2C, PWM.
F4PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
F5PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC.
F6PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
F7VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
G1PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, I2C2_SMBA. Supported peripheral buses: UART, SPI, I2C.
G2VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
G3PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK, I2C2_SCL. Supported peripheral buses: SPI, I2C, PWM.
G4PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
G5PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC, PWM.
G6PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, PWM.
G7PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
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