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STM32F205REY6TR (WLCSP-64) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F205REY6TR

STID: C2053088WLCSP-64 · 66 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F205REY6TR (WLCSP-64)A1PF1A2PF2A3PF3A4PF4A5PF5A6PF12A7PF13A8PF14A9PF15B1VSSB2PA13 (JTMSSWB3PC10B4PB4B5PB6B6BOOT0B7PB8B8PC13B9PC14/OSC32_IC1PA12C2VCAP_2C3PC11C7PD2C8IRROFFC9IOC9D1PD15D2PD0D3PD1D7PE10D8PE11D9PE12E1VDDE2PA8E3PA9J9PA2J8PA4J7PA7J6PB0J5PB1J4PB2/BOOT1(PBJ3VCAP_1J2PB11J1PB12H9VSSH8PA1H7REGOFFH6PA5H5PA6H4PC4H3PB10H2PB13H1PB14G9PC0G8PC3G7PA3G3PC5G2PC6G1PB15F9PH1/OSC_OUT F8PC1F7VREF+F3PC8F2PC7F1VSSE9PH0/OSC_IN (E8NRSTE7PA0WKUP - (PGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.848.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1A2B2C2D2E2F2G2H2J2A3B3C3D3E3F3G3H3J3A4B4H4J4A5B5H5J5A6B6H6J6A7B7C7D7E7F7G7H7J7A8B8C8D8E8F8G8H8J8A9B9C9D9E9F9G9H9J9E=3.60mm · Pitch e=0.40mmD=3.90mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.60mm × 3.90mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (66/66)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PF1I/OMultiplexed I/O & Peripheral Pin PF1 (General)
A2PF2I/OMultiplexed I/O & Peripheral Pin PF2 (General)
A3PF3I/OMultiplexed I/O & Peripheral Pin PF3 (General)
A4PF4I/OMultiplexed I/O & Peripheral Pin PF4 (General)
A5PF5I/OMultiplexed I/O & Peripheral Pin PF5 (General)
A6PF12I/OMultiplexed I/O & Peripheral Pin PF12 (General)
A7PF13I/OMultiplexed I/O & Peripheral Pin PF13 (General)
A8PF14I/OMultiplexed I/O & Peripheral Pin PF14 (General)
A9PF15I/OMultiplexed I/O & Peripheral Pin PF15 (General)
B1VSSGNDGround Reference Pin (VSS)
B2PA13 (JTMSSWDIO) -I/OMultiplexed I/O & Peripheral Pin PA13 (JTMSSWDIO) - (SWD/JTAG)
B3PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
B4PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, PWM, SWD/JTAG)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C, CAN)
B6BOOT0IInput-Only Pin BOOT0 (General)
B7PB8I/OMultiplexed I/O & Peripheral Pin PB8 (UART, PWM, CAN)
B8PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
B9PC14/OSC32_IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14/OSC32_IN (PC14) (RTC/CLK)
C1PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART)
C2VCAP_2I/OMultiplexed I/O & Peripheral Pin VCAP_2 (General)
C3PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART)
C7PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
C8IRROFFI/OMultiplexed I/O & Peripheral Pin IRROFF (General)
C9IOC9I/OGeneral Purpose Digital I/O Pin IOC9
D1PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
D2PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
D3PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
D7PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
D8PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
D9PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
E1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E2PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, PWM, RTC/CLK)
E3PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C)
E7PA0WKUP - (PA0)I/OMultiplexed I/O & Peripheral Pin PA0WKUP - (PA0) (UART, ADC, PWM)
E8NRSTISystem Enable & Hardware Reset (NRST)
E9PH0/OSC_IN (PH0)I/OMultiplexed I/O & Peripheral Pin PH0/OSC_IN (PH0) (RTC/CLK)
F1VSSGNDGround Reference Pin (VSS)
F2PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
F3PC8I/OMultiplexed I/O & Peripheral Pin PC8 (PWM)
F7VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
F8PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
F9PH1/OSC_OUT (PH1)I/OMultiplexed I/O & Peripheral Pin PH1/OSC_OUT (PH1) (RTC/CLK)
G1PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM, RTC/CLK)
G2PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
G3PC5I/OMultiplexed I/O & Peripheral Pin PC5 (ADC)
G7PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
G8PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI, ADC)
G9PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
H1PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI)
H2PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, CAN)
H3PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, I2C)
H4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
H5PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
H6PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
H7REGOFFI/OMultiplexed I/O & Peripheral Pin REGOFF (General)
H8PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
H9VSSGNDGround Reference Pin (VSS)
J1PB12I/OMultiplexed I/O & Peripheral Pin PB12 (SPI, I2C)
J2PB11I/OMultiplexed I/O & Peripheral Pin PB11 (I2C, PWM)
J3VCAP_1I/OMultiplexed I/O & Peripheral Pin VCAP_1 (General)
J4PB2/BOOT1(PB2)I/OMultiplexed I/O & Peripheral Pin PB2/BOOT1(PB2) (General)
J5PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
J6PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
J7PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
J8PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
J9PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
PIN A1 PF1
I/O
Multiplexed I/O & Peripheral Pin PF1 (General)
Design note: Signal terminal PF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F205REY6TR (ST · WLCSP-64)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F205REY6TR (WLCSP-64) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F205REY6TR (WLCSP-64) - 2. Standard Pinout (Top View)
True package pinout (66 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F205REY6TR (WLCSP-64) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F205REY6TR (WLCSP-64) - 4. Package Dimensions (D×E×A)
WLCSP-64 · 3.60×3.90mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F205REY6TR (WLCSP-64) - 5. Recommended Land Pattern
IPC-7351B Footprint (66 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F205REY6TR (WLCSP-64) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for STM32F207 / STM32F205
P41 · p41_fig01EXACT PACKAGE
STM32F205REY6TR (WLCSP-64) — Figure 10. STM32F20x LQFP64 pinout
Figure 10. STM32F20x LQFP64 pinout
P41 · p41_fig02EXACT PACKAGE
STM32F205REY6TR (WLCSP-64) — Figure 11. STM32F20x WLCSP64+2 ballout 1 2 3 8
Figure 11. STM32F20x WLCSP64+2 ballout 1 2 3 8
P151 · p151_fig01EXACT PACKAGE
STM32F205REY6TR (WLCSP-64) — Figure 80. WLCSP64+2 outline
Figure 80. WLCSP64+2 outline
P152 · p152_fig01EXACT PACKAGE
STM32F205REY6TR (WLCSP-64) — Figure 81. WLCSP64+2 recommended footprint
Figure 81. WLCSP64+2 recommended footprint
P1 · p01_fig01881×566px
STM32F205REY6TR (WLCSP-64) —   Up to 140 I/O ports with interrupt capability: - Up to 136 fast I/Os up to 60 MHz - Up to 138 5 V-tolerant I/Os
  Up to 140 I/O ports with interrupt capability: - Up to 136 fast I/Os up to 60 MHz - Up to 138 5 V-tolerant I/Os
P41 · p41_fig01P41
STM32F205REY6TR (WLCSP-64) — Datasheet Page 41 (p41_fig01)
Datasheet Page 41 (p41_fig01)
P42 · p42_fig011546×1466px
STM32F205REY6TR (WLCSP-64) — Figure 12. STM32F20x LQFP100 pinout
Figure 12. STM32F20x LQFP100 pinout
P68 · p68_fig011751×1623px
STM32F205REY6TR (WLCSP-64) — Figure 19. Power supply scheme VBAT
Figure 19. Power supply scheme VBAT
P68 · p68_fig01P68
STM32F205REY6TR (WLCSP-64) — Datasheet Page 68 (p68_fig01)
Datasheet Page 68 (p68_fig01)
P90 · p90_fig011546×484px
STM32F205REY6TR (WLCSP-64) — Figure 32. Typical application with an 8 MHz crystal
Figure 32. Typical application with an 8 MHz crystal
P91 · p91_fig011751×593px
STM32F205REY6TR (WLCSP-64) — Figure 33. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors
Figure 33. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors
P149 · p149_fig011546×1060px
STM32F205REY6TR (WLCSP-64) — Figure 78. LQFP64 recommended footprint
Figure 78. LQFP64 recommended footprint
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (STM32F205REY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F205REY6TR (WLCSP-64) is a 64-pin embedded microcontroller unit (mcu) featuring a 3.90 × 3.60 × 0.57 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, CAN, DAC, RTC/CLK, SPI, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
120 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
38 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
3.90 × 3.60 × 0.57 mm (A1=0.19 mm)
Package family: WLCSP (WLCSP-64)
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, CAN, DAC, RTC/CLK, SPI, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PB2/BOOT1(PB2)): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol66 auto-grouped pins
OK
IPC-7351B Land Pattern66 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-64)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.90 × 3.60 mm
Height (A) & Pitch (e)IPC-7351B
A=0.57mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.22 mm
Pins / Total PadsTopology
66P / 66Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-64
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F205REY6TR (WLCSP-64)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F205REY6TR (WLCSP-64)?

Manufactured by ST, the STM32F205REY6TR is housed in a WLCSP-64 package with 66 pins and a 0.40 mm lead pitch. Key pins include: A1 (PF1: Multiplexed I/O & Peripheral Pin PF1 (General)), A2 (PF2: Multiplexed I/O & Peripheral Pin PF2 (General)), A3 (PF3: Multiplexed I/O & Peripheral Pin PF3 (General)), A4 (PF4: Multiplexed I/O & Peripheral Pin PF4 (General)), A5 (PF5: Multiplexed I/O & Peripheral Pin PF5 (General)), A6 (PF12: Multiplexed I/O & Peripheral Pin PF12 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32F205REY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F205REY6TR (WLCSP-64) has a nominal body envelope of 3.60 × 3.90 mm, pitch e = 0.40 mm, and 66 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F205REY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F205REY6TR (ST, WLCSP-64) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (66 pins) & STM32F207 / STM32F205 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PF1Digital_IOSignal terminal PF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General.
A2PF2Digital_IOSignal terminal PF2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General.
A3PF3Digital_IOSignal terminal PF3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General.
A4PF4Digital_IOSignal terminal PF4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
A5PF5Digital_IOSignal terminal PF5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
A6PF12Digital_IOSignal terminal PF12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF12. Supported peripheral buses: General.
A7PF13Digital_IOSignal terminal PF13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF13. Supported peripheral buses: General.
A8PF14Digital_IOSignal terminal PF14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF14. Supported peripheral buses: General.
A9PF15Digital_IOSignal terminal PF15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF15. Supported peripheral buses: General.
B1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B2PA13 (JTMSSWDIO) -Digital_IOSignal terminal PA13 (JTMSSWDIO) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMSSWDIO) -. Supported peripheral buses: SWD/JTAG.
B3PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCKI2S3SCK. Supported peripheral buses: UART, SPI.
B4PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: SPI, PWM, SWD/JTAG.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: I2C, CAN.
B6BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
B7PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: UART, PWM, CAN.
B8PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
B9PC14/OSC32_IN (PC14)Digital_IOSignal terminal PC14/OSC32_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14/OSC32_IN (PC14). Supported peripheral buses: RTC/CLK.
C1PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART.
C2VCAP_2Digital_IOSignal terminal VCAP_2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_2. Supported peripheral buses: General.
C3PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: UART.
C7PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
C8IRROFFDigital_IOSignal terminal IRROFF (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: IRROFF. Supported peripheral buses: General.
C9IOC9Digital_IOGeneral Purpose Digital I/O Pin IOC9
D1PD15Digital_IOSignal terminal PD15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General.
D2PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
D3PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
D7PE10Digital_IOSignal terminal PE10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE10. Supported peripheral buses: General.
D8PE11Digital_IOSignal terminal PE11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE11. Supported peripheral buses: General.
D9PE12Digital_IOSignal terminal PE12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE12. Supported peripheral buses: General.
E1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E2PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, PWM, RTC/CLK.
E3PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, I2C.
E7PA0WKUP - (PA0)Digital_IOSignal terminal PA0WKUP - (PA0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0WKUP - (PA0). Supported peripheral buses: UART, ADC, PWM.
E8NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E9PH0/OSC_IN (PH0)Digital_IOSignal terminal PH0/OSC_IN (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0/OSC_IN (PH0). Supported peripheral buses: RTC/CLK.
F1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F2PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
F3PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: PWM.
F7VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
F8PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
F9PH1/OSC_OUT (PH1)Digital_IOSignal terminal PH1/OSC_OUT (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1/OSC_OUT (PH1). Supported peripheral buses: RTC/CLK.
G1PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSII2S2SD. Supported peripheral buses: SPI, PWM, RTC/CLK.
G2PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
G3PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC.
G7PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
G8PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSII2S2SD. Supported peripheral buses: SPI, ADC.
G9PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
H1PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOTIM1CH2N. Supported peripheral buses: UART, SPI.
H2PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKI2S2SCK. Supported peripheral buses: UART, SPI, CAN.
H3PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKI2S2SCK. Supported peripheral buses: SPI, I2C.
H4PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
H5PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOTIM8BKIN. Supported peripheral buses: SPI, ADC, PWM.
H6PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC, PWM.
H7REGOFFDigital_IOSignal terminal REGOFF (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: REGOFF. Supported peripheral buses: General.
H8PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
H9VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
J1PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSI2S2WS. Supported peripheral buses: SPI, I2C.
J2PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: I2C, PWM.
J3VCAP_1Digital_IOSignal terminal VCAP_1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_1. Supported peripheral buses: General.
J4PB2/BOOT1(PB2)Digital_IOSignal terminal PB2/BOOT1(PB2) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2/BOOT1(PB2). Supported peripheral buses: General.
J5PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
J6PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
J7PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSITIM8CH1N. Supported peripheral buses: SPI, ADC, PWM.
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