MIC2043-2BTS-TR (TSSOP-14) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of MIC2043-2BTS-TR (TSSOP-14)?

Manufactured by MICROCHIP, the MIC2043-2BTS-TR is housed in a TSSOP-14 package with 14 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 8V to 5.5V. Key pins include: 1 (PWRGD: Multiplexed I/O & Peripheral Pin PWRGD (General)), 2 (EN: System Enable & Hardware Reset (EN)), 3 (/FAULT: Multiplexed I/O & Peripheral Pin /FAULT (General)), 4 (UVLOIN: Multiplexed I/O & Peripheral Pin UVLOIN (General)), 5 (GND: Ground Reference Pin (GND)), 6 (ILIM: Multiplexed I/O & Peripheral Pin ILIM (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for MIC2043-2BTS-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC2043-2BTS-TR (TSSOP-14) has a nominal body envelope of 4.40 × 5.00 mm, pitch e = 0.65 mm, and 14 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC2043-2BTS-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC2043-2BTS-TR (MICROCHIP, TSSOP-14) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 4.40mm × 5.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (14/14)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	PWRGD	I/O	Multiplexed I/O & Peripheral Pin PWRGD (General)
2	EN	I	System Enable & Hardware Reset (EN)
3	/FAULT	I/O	Multiplexed I/O & Peripheral Pin /FAULT (General)
4	UVLOIN	I/O	Multiplexed I/O & Peripheral Pin UVLOIN (General)
5	GND	GND	Ground Reference Pin (GND)
6	ILIM	I/O	Multiplexed I/O & Peripheral Pin ILIM (General)
7	VBIAS	I/O	Multiplexed I/O & Peripheral Pin VBIAS (General)
8	VIN	Power	Regulated Power Output (VIN — 8V to 5.5V)
9	SLEW	I/O	Multiplexed I/O & Peripheral Pin SLEW (General)
10	VOUT	Power	Regulated Power Output (VOUT — 8V to 5.5V)
11	VOUT	Power	Regulated Power Output (VOUT — 8V to 5.5V)
12	VIN	Power	Regulated Power Output (VIN — 8V to 5.5V)
13	PGREF	I/O	Multiplexed I/O & Peripheral Pin PGREF (General)
14	VOUT	Power	Regulated Power Output (VOUT — 8V to 5.5V)

PIN 1 PWRGD

I/O

Multiplexed I/O & Peripheral Pin PWRGD (General)

Design note: Power-Good Output: Active high open-drain This pin asserts high when the , . voltageatPGREFexceedsitsthreshold .

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

MIC2043-2BTS-TR (TSSOP-14) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

MIC2043-2BTS-TR (TSSOP-14) - 2. Standard Pinout (Top View)

True package pinout (14 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

MIC2043-2BTS-TR (TSSOP-14) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

MIC2043-2BTS-TR (TSSOP-14) - 4. Package Dimensions (D×E×A)

TSSOP-14 · 4.40×5.00mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

MIC2043-2BTS-TR (TSSOP-14) - 5. Recommended Land Pattern

IPC-7351B Footprint (14 Pads)Expand ›

6. Application SchematicSCHEMATIC

MIC2043-2BTS-TR (TSSOP-14) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)

Showing 1–7 of 7 uncropped original figures for MIC2042 / MIC2043

P2 · p02_fig02EXACT PACKAGE

1 PWRGD | EN | /FAULT | UVLOIN | GND | ILIM | VBIAS | 14 VOUT | PGREF | VIN | VOUT | VOUT | SLEW | VIN | 13 | 12 | 11 | 10 | 9 | 8 | 2 | 3 | 4 | 5 | 6 | 7 | 14-Pin TSSOP (TS)

P1 · p01_fig012038×1825px

Typical Application

P1 · p01_fig021654×667px

Typical Application

P14 · p14_fig011603×646px

Figure 4. Lower UVLO Setting

P15 · p15_fig011546×906px

MIC2042/2043 Micrel

P15 · p15_fig021151×825px

MIC2043-2BTS-TR (TSSOP-14) — 1.10 MAX (0.043) | 0.15 (0.006) 0.05 (0.002) | 1.00 (0.039) REF 0.65 BSC (0.026) 8° 0° | 6.4 BSC (0.252) | 5.10 (0.200) 4.90 (0.193) 0.20 (0.008) 0.09 (0.003) | 0.70 (0.028) 0.50 (0.020) | DIMENSIONS: | MM (INCH) | 4.50 (0.177) 4.30 (0.169)

1.10 MAX (0.043) | 0.15 (0.006) 0.05 (0.002) | 1.00 (0.039) REF 0.65 BSC (0.026) 8° 0° | 6.4 BSC (0.252) | 5.10 (0.200) 4.90 (0.193) 0.20 (0.008) 0.09 (0.003) | 0.70 (0.028) 0.50 (0.020) | DIMENSIONS: | MM (INCH) | 4.50 (0.177) 4.30 (0.169)

P2 · p02_fig01All Packages in PDF

Pin Configuration

Technical Specifications & Part Details (MIC2043-2BTS-TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:MIC2043-2BTS-TR (TSSOP-14) is a 14-pin standard electronic & interconnect component featuring a 5.00 × 4.40 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 8V to 5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB interfaces.

Operating Supply VoltageV_CC / V_DD

8V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

DC / Broadband Passive

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

0.5A

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

5.00 × 4.40 × 1.00 mm (A1=0.10 mm)

Package family: TSSOP (TSSOP-14)

Pin Count & Lead PitchN / e

14 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol14 auto-grouped pins

IPC-7351B Land Pattern14 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-14)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

5.00 × 4.40 mm

Height (A) & Pitch (e)IPC-7351B

A=1.00mm · e=0.65mm

Pad Size (W × L)Level B

0.42 × 1.45 mm

Pins / Total PadsTopology

14P / 14Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit TSSOP-14	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MIC2043-2BTS-TR (TSSOP-14)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MIC2043-2BTS-TR (TSSOP-14)?

Manufactured by MICROCHIP, the MIC2043-2BTS-TR is housed in a TSSOP-14 package with 14 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 8V to 5.5V. Key pins include: 1 (PWRGD: Multiplexed I/O & Peripheral Pin PWRGD (General)), 2 (EN: System Enable & Hardware Reset (EN)), 3 (/FAULT: Multiplexed I/O & Peripheral Pin /FAULT (General)), 4 (UVLOIN: Multiplexed I/O & Peripheral Pin UVLOIN (General)), 5 (GND: Ground Reference Pin (GND)), 6 (ILIM: Multiplexed I/O & Peripheral Pin ILIM (General)).

What are the IPC-7351B PCB Footprint dimensions for MIC2043-2BTS-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC2043-2BTS-TR (TSSOP-14) has a nominal body envelope of 4.40 × 5.00 mm, pitch e = 0.65 mm, and 14 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC2043-2BTS-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC2043-2BTS-TR (MICROCHIP, TSSOP-14) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (14 pins) & MIC2042 / MIC2043 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	PWRGD	Open_Drain	Signal terminal PWRGD (I/O, 8V to 5.5V domain). Multiplexed alternate functions: PWRGD. Supported peripheral buses: General.
2	EN	Digital_IO	Chip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset.
3	/FAULT	Open_Drain	Signal terminal /FAULT (I/O, 8V to 5.5V domain). Multiplexed alternate functions: /FAULT. Supported peripheral buses: General.
4	UVLOIN	Digital_IO	Signal terminal UVLOIN (I/O, 8V to 5.5V domain). Multiplexed alternate functions: UVLOIN. Supported peripheral buses: General.
5	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
6	ILIM	Digital_IO	Signal terminal ILIM (I/O, 8V to 5.5V domain). Multiplexed alternate functions: ILIM. Supported peripheral buses: General.
7	VBIAS	Digital_IO	Signal terminal VBIAS (I/O, 8V to 5.5V domain). Multiplexed alternate functions: VBIAS. Supported peripheral buses: General.
8	VIN	Power_Out	Regulated power output rail (VIN) operating in the 8V to 5.5V domain (Max rating: 8.0V).
9	SLEW	Digital_IO	Signal terminal SLEW (I/O, 8V to 5.5V domain). Multiplexed alternate functions: SLEW. Supported peripheral buses: General.
10	VOUT	Power_Out	Regulated power output rail (VOUT) operating in the 8V to 5.5V domain (Max rating: 8.0V).
11	VOUT	Power_Out	Regulated power output rail (VOUT) operating in the 8V to 5.5V domain (Max rating: 8.0V).
12	VIN	Power_Out	Regulated power output rail (VIN) operating in the 8V to 5.5V domain (Max rating: 8.0V).
13	PGREF	Digital_IO	Signal terminal PGREF (I/O, 8V to 5.5V domain). Multiplexed alternate functions: PGREF. Supported peripheral buses: General.
14	VOUT	Power_Out	Regulated power output rail (VOUT) operating in the 8V to 5.5V domain (Max rating: 8.0V).

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