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STM32L471QEI7 (UFBGA-132) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L471QEI7

STID: C1342750UFBGA-132 · 132 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L471QEI7 (UFBGA-132)A1PE3A2PE1A3PB8A4BOOT0A5PD7A6PD5A7PB4 (NJTRST)A8PB3 (JTDO - A9PA15(JTDI)A10PA14 (JTCKSWA11PA13 (JTMSSWA12PA12B1PE4B2PE2B3PB9B4PB7B5PB6B6PD6B7PD4B8PD3B9PD1B10PC12B11PC10B12PA11C1PC13C2PE5C3PE0C4VDDC5PB5C6PG14C7PG13C8PD2C9PD0C10PC11C11VDDC12PA10D1PC14 - OSC32D2PE6D3VSSD4PF2D5PF1D6PF0D7PG12D8PG10D9PG9D10PA9D11PA8D12PC9E1IOE1E2VBATE3VSSE4PF3E9PG5E10PC8E11PC7E12PC6F1PH0OSC IN -_F2VSSF3PF4F4PF5F6VSSF7VSSF9PG3F10PG4F11VSSF12VSSM12PE15M11PE14M10PE13M9PE11M8PE9M7PE7M6PB1M5PB0M4OPAMP2_VINMM3OPAMP1_VINMM2PA1M1VDDAL12PB12L11PB11L10PB10L9PE12L8PE10L7PE8L6PB2L5PC5L4PA6L3PA3L2PA0L1VREF+K12PB13K11PB14K10PB15K9PD8K8PD9K7PF13K6PF11K5PC4K4PA5K3PA2K2PC3K1PG15J12PD10J11PD11J10PD12J9PF15J8PF14J7PF12J6PG8J5PA7J4PA4J3PC2J2PC1J1VSSA/VREF -H12PD13H11PD14H10PD15H9PG0H4PG7H3VDDH2NRSTH1PC0G12VDDG11VDDG10PG2G9PG1G7VDDIO2G6VDDG4PG6G3PG11G2VDDG1PH1OSC OUT -Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.888.983.878.773.768.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6-73.7-78.7-83.8-88.9mm
2. 2D FOOTPRINT
A1A2A3A4A5A6A7A8A9A10A11A12B1B2B3B4B5B6B7B8B9B10B11B12C1C2C3C4C5C6C7C8C9C10C11C12D1D2D3D4D5D6D7D8D9D10D11D12E1E2E3E4E9E10E11E12F1F2F3F4F6F7F9F10F11F12G1G2G3G4G6G7G9G10G11G12H1H2H3H4H9H10H11H12J1J2J3J4J5J6J7J8J9J10J11J12K1K2K3K4K5K6K7K8K9K10K11K12L1L2L3L4L5L6L7L8L9L10L11L12M1M2M3M4M5M6M7M8M9M10M11M12E=7.00mm · Pitch e=0.50mmD=7.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (132/132)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
A2PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
A3PB8I/OMultiplexed I/O & Peripheral Pin PB8 (PWM, CAN)
A4BOOT0IInput-Only Pin BOOT0 (General)
A5PD7I/OMultiplexed I/O & Peripheral Pin PD7 (UART)
A6PD5I/OMultiplexed I/O & Peripheral Pin PD5 (UART)
A7PB4 (NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4 (NJTRST) (UART, SPI, SWD/JTAG)
A8PB3 (JTDO - TRACESWO)I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO - TRACESWO) (UART, SPI, PWM, SWD/JTAG)
A9PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG)
A10PA14 (JTCKSWCLK) -I/OMultiplexed I/O & Peripheral Pin PA14 (JTCKSWCLK) - (SWD/JTAG)
A11PA13 (JTMSSWDIO) -I/OMultiplexed I/O & Peripheral Pin PA13 (JTMSSWDIO) - (SWD/JTAG)
A12PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART, CAN)
B1PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
B2PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
B3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (I2C, CAN)
B4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART)
B6PD6I/OMultiplexed I/O & Peripheral Pin PD6 (UART)
B7PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART, SPI)
B8PD3I/OMultiplexed I/O & Peripheral Pin PD3 (UART, SPI)
B9PD1I/OMultiplexed I/O & Peripheral Pin PD1 (SPI, CAN)
B10PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI)
B11PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
B12PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, PWM)
C1PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
C2PE5I/OMultiplexed I/O & Peripheral Pin PE5 (SPI)
C3PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
C4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
C5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C)
C6PG14I/OMultiplexed I/O & Peripheral Pin PG14 (I2C)
C7PG13I/OMultiplexed I/O & Peripheral Pin PG13 (I2C)
C8PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
C9PD0I/OMultiplexed I/O & Peripheral Pin PD0 (SPI, CAN)
C10PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI)
C11VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
C12PA10I/OMultiplexed I/O & Peripheral Pin PA10 (PWM)
D1PC14 - OSC32_IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)
D2PE6I/OMultiplexed I/O & Peripheral Pin PE6 (RTC/CLK)
D3VSSGNDGround Reference Pin (VSS)
D4PF2I/OMultiplexed I/O & Peripheral Pin PF2 (I2C)
D5PF1I/OMultiplexed I/O & Peripheral Pin PF1 (I2C)
D6PF0I/OMultiplexed I/O & Peripheral Pin PF0 (I2C)
D7PG12I/OMultiplexed I/O & Peripheral Pin PG12 (UART)
D8PG10I/OMultiplexed I/O & Peripheral Pin PG10 (UART)
D9PG9I/OMultiplexed I/O & Peripheral Pin PG9 (SPI)
D10PA9I/OMultiplexed I/O & Peripheral Pin PA9 (PWM)
D11PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
D12PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E1IOE1I/OGeneral Purpose Digital I/O Pin IOE1
E2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
E3VSSGNDGround Reference Pin (VSS)
E4PF3I/OMultiplexed I/O & Peripheral Pin PF3 (ADC)
E9PG5I/OMultiplexed I/O & Peripheral Pin PG5 (UART, SPI)
E10PC8I/OMultiplexed I/O & Peripheral Pin PC8 (PWM)
E11PC7I/OMultiplexed I/O & Peripheral Pin PC7 (PWM)
E12PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
F1PH0OSC IN -_ (PH0)I/OMultiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (RTC/CLK)
F2VSSGNDGround Reference Pin (VSS)
F3PF4I/OMultiplexed I/O & Peripheral Pin PF4 (ADC)
F4PF5I/OMultiplexed I/O & Peripheral Pin PF5 (ADC)
F6VSSGNDGround Reference Pin (VSS)
F7VSSGNDGround Reference Pin (VSS)
F9PG3I/OMultiplexed I/O & Peripheral Pin PG3 (SPI)
F10PG4I/OMultiplexed I/O & Peripheral Pin PG4 (SPI)
F11VSSGNDGround Reference Pin (VSS)
F12VSSGNDGround Reference Pin (VSS)
G1PH1OSC OUT -_ (PH1)I/OMultiplexed I/O & Peripheral Pin PH1OSC OUT -_ (PH1) (RTC/CLK)
G2VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G3PG11I/OMultiplexed I/O & Peripheral Pin PG11 (UART)
G4PG6I/OMultiplexed I/O & Peripheral Pin PG6 (UART, I2C)
G6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G7VDDIO2PowerPower Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))
G9PG1I/OMultiplexed I/O & Peripheral Pin PG1 (General)
G10PG2I/OMultiplexed I/O & Peripheral Pin PG2 (SPI)
G11VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G12VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
H1PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
H2NRSTISystem Enable & Hardware Reset (NRST)
H3VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
H4PG7I/OMultiplexed I/O & Peripheral Pin PG7 (I2C)
H9PG0I/OMultiplexed I/O & Peripheral Pin PG0 (General)
H10PD15I/OMultiplexed I/O & Peripheral Pin PD15 (PWM)
H11PD14I/OMultiplexed I/O & Peripheral Pin PD14 (PWM)
H12PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
J1VSSA/VREF -GNDGround Reference Pin (VSSA/VREF -)
J2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
J3PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
J4PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
J5PA7I/OMultiplexed I/O & Peripheral Pin PA7 (ADC, PWM)
J6PG8I/OMultiplexed I/O & Peripheral Pin PG8 (I2C)
J7PF12I/OMultiplexed I/O & Peripheral Pin PF12 (General)
J8PF14I/OMultiplexed I/O & Peripheral Pin PF14 (General)
J9PF15I/OMultiplexed I/O & Peripheral Pin PF15 (General)
J10PD12I/OMultiplexed I/O & Peripheral Pin PD12 (UART, PWM)
J11PD11I/OMultiplexed I/O & Peripheral Pin PD11 (UART, I2C)
J12PD10I/OMultiplexed I/O & Peripheral Pin PD10 (UART, SPI)
K1PG15I/OMultiplexed I/O & Peripheral Pin PG15 (I2C)
K2PC3I/OMultiplexed I/O & Peripheral Pin PC3 (I2C, ADC)
K3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
K4PA5I/OMultiplexed I/O & Peripheral Pin PA5 (ADC, DAC, PWM)
K5PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
K6PF11I/OMultiplexed I/O & Peripheral Pin PF11 (General)
K7PF13I/OMultiplexed I/O & Peripheral Pin PF13 (General)
K8PD9I/OMultiplexed I/O & Peripheral Pin PD9 (UART)
K9PD8I/OMultiplexed I/O & Peripheral Pin PD8 (UART)
K10PB15I/OMultiplexed I/O & Peripheral Pin PB15 (PWM, RTC/CLK)
K11PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, I2C, PWM)
K12PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
L1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
L2PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
L3PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
L4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, ADC)
L5PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
L6PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C, RTC/CLK)
L7PE8I/OMultiplexed I/O & Peripheral Pin PE8 (PWM)
L8PE10I/OMultiplexed I/O & Peripheral Pin PE10 (PWM)
L9PE12I/OMultiplexed I/O & Peripheral Pin PE12 (PWM)
L10PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, SPI, PWM)
L11PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, PWM)
L12PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, I2C)
M1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
M2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
M3OPAMP1_VINMPowerPower Supply Input (OPAMP1_VINM — 3.3V VDD (Max 4.0V))
M4OPAMP2_VINMPowerPower Supply Input (OPAMP2_VINM — 3.3V VDD (Max 4.0V))
M5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, ADC, PWM)
M6PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
M7PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
M8PE9I/OMultiplexed I/O & Peripheral Pin PE9 (PWM)
M9PE11I/OMultiplexed I/O & Peripheral Pin PE11 (PWM)
M10PE13I/OMultiplexed I/O & Peripheral Pin PE13 (PWM)
M11PE14I/OMultiplexed I/O & Peripheral Pin PE14 (SPI, PWM)
M12PE15I/OMultiplexed I/O & Peripheral Pin PE15 (SPI)
PIN A1 PE3
I/O
Multiplexed I/O & Peripheral Pin PE3 (General)
Design note: Signal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L471QEI7 (ST · UFBGA-132)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L471QEI7 (UFBGA-132) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L471QEI7 (UFBGA-132) - 2. Standard Pinout (Top View)
True package pinout (132 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L471QEI7 (UFBGA-132) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L471QEI7 (UFBGA-132) - 4. Package Dimensions (D×E×A)
UFBGA-132 · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L471QEI7 (UFBGA-132) - 5. Recommended Land Pattern
IPC-7351B Footprint (132 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L471QEI7 (UFBGA-132) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for STM32L471
P60 · p60_fig01EXACT PACKAGE
STM32L471QEI7 (UFBGA-132) — Figure 7. STM32L471Zx UFBGA144 ballout(1)
Figure 7. STM32L471Zx UFBGA144 ballout(1)
P60 · p60_fig02EXACT PACKAGE
STM32L471QEI7 (UFBGA-132) — VREF+ VDDA PA1 PA6 PB2 PE11 PB11 PB12 PD8 PD9
VREF+ VDDA PA1 PA6 PB2 PE11 PB11 PB12 PD8 PD9
P1 · p01_fig011269×469px
STM32L471QEI7 (UFBGA-132) — • Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
• Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
P59 · p59_fig011546×1366px
STM32L471QEI7 (UFBGA-132) — Figure 6. STM32L471Zx LQFP144 pinout(1) PG11 PG12 PG13 PG14 VSS VDDIO2 PG15 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS VDD 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Figure 6. STM32L471Zx LQFP144 pinout(1) PG11 PG12 PG13 PG14 VSS VDDIO2 PG15 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS VDD 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
P60 · p60_fig02P60
STM32L471QEI7 (UFBGA-132) — Datasheet Page 60 (p60_fig02)
Datasheet Page 60 (p60_fig02)
P62 · p62_fig011711×906px
STM32L471QEI7 (UFBGA-132) — 62/229 DS10741 Rev 3
62/229 DS10741 Rev 3
P62 · p62_fig01P62
STM32L471QEI7 (UFBGA-132) — Datasheet Page 62 (p62_fig01)
Datasheet Page 62 (p62_fig01)
P96 · p96_fig011751×1932px
STM32L471QEI7 (UFBGA-132) — Figure 14. Power supply scheme
Figure 14. Power supply scheme
P96 · p96_fig01P96
STM32L471QEI7 (UFBGA-132) — Datasheet Page 96 (p96_fig01)
Datasheet Page 96 (p96_fig01)
P129 · p129_fig011546×702px
STM32L471QEI7 (UFBGA-132) — Figure 19. Typical application with an 8 MHz crystal
Figure 19. Typical application with an 8 MHz crystal
P130 · p130_fig011546×702px
STM32L471QEI7 (UFBGA-132) — Figure 20. Typical application with a 32.768 kHz crystal
Figure 20. Typical application with a 32.768 kHz crystal
P214 · p214_fig011752×2294px
STM32L471QEI7 (UFBGA-132) — Figure 56. UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
Figure 56. UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (STM32L471QEI7)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L471QEI7 (UFBGA-132) is a 132-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, CAN, PWM, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
80 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
101 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.60 mm (A1=0.20 mm)
Package family: BGA (UFBGA-132)
Pin Count & Lead PitchN / e
132 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, CAN, PWM, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol132 auto-grouped pins
OK
IPC-7351B Land Pattern132 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-132)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.60mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.28 mm
Pins / Total PadsTopology
132P / 132Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-132
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L471QEI7 (UFBGA-132)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L471QEI7 (UFBGA-132)?

Manufactured by ST, the STM32L471QEI7 is housed in a UFBGA-132 package with 132 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), A2 (PE1: Multiplexed I/O & Peripheral Pin PE1 (General)), A3 (PB8: Multiplexed I/O & Peripheral Pin PB8 (PWM, CAN)), A4 (BOOT0: Input-Only Pin BOOT0 (General)), A5 (PD7: Multiplexed I/O & Peripheral Pin PD7 (UART)), A6 (PD5: Multiplexed I/O & Peripheral Pin PD5 (UART)).

What are the IPC-7351B PCB Footprint dimensions for STM32L471QEI7?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L471QEI7 (UFBGA-132) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 132 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L471QEI7?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L471QEI7 (ST, UFBGA-132) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (132 pins) & STM32L471 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
A2PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
A3PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: PWM, CAN.
A4BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A5PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: UART.
A6PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: UART.
A7PB4 (NJTRST)Digital_IOSignal terminal PB4 (NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOSPI3MISO. Supported peripheral buses: UART, SPI, SWD/JTAG.
A8PB3 (JTDO - TRACESWO)Digital_IOSignal terminal PB3 (JTDO - TRACESWO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI, PWM, SWD/JTAG.
A9PA15(JTDI)Digital_IOSignal terminal PA15(JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_NSS. Supported peripheral buses: UART, SPI, SWD/JTAG.
A10PA14 (JTCKSWCLK) -Digital_IOSignal terminal PA14 (JTCKSWCLK) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (JTCKSWCLK) -. Supported peripheral buses: SWD/JTAG.
A11PA13 (JTMSSWDIO) -Digital_IOSignal terminal PA13 (JTMSSWDIO) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMSSWDIO) -. Supported peripheral buses: SWD/JTAG.
A12PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART, CAN.
B1PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
B2PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
B3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: I2C, CAN.
B4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART.
B6PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: UART.
B7PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: UART, SPI.
B8PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI.
B9PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI, CAN.
B10PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSIUSART3CK. Supported peripheral buses: UART, SPI.
B11PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCKUSART3TX. Supported peripheral buses: UART, SPI.
B12PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: UART, PWM.
C1PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
C2PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: SPI.
C3PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
C4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSIUSART1CK. Supported peripheral buses: UART, SPI, I2C.
C6PG14Digital_IOSignal terminal PG14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG14. Supported peripheral buses: I2C.
C7PG13Digital_IOSignal terminal PG13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG13. Supported peripheral buses: I2C.
C8PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
C9PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI, CAN.
C10PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISOUSART3RX. Supported peripheral buses: UART, SPI.
C11VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C12PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: PWM.
D1PC14 - OSC32_IN (PC14)Digital_IOSignal terminal PC14 - OSC32_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN (PC14). Supported peripheral buses: RTC/CLK.
D2PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: RTC/CLK.
D3VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D4PF2Digital_IOSignal terminal PF2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: I2C.
D5PF1Digital_IOSignal terminal PF1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: I2C.
D6PF0Digital_IOSignal terminal PF0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF0. Supported peripheral buses: I2C.
D7PG12Digital_IOSignal terminal PG12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG12. Supported peripheral buses: UART.
D8PG10Digital_IOSignal terminal PG10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG10. Supported peripheral buses: UART.
D9PG9Digital_IOSignal terminal PG9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCKUSART1TX. Supported peripheral buses: SPI.
D10PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: PWM.
D11PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
D12PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E1IOE1Digital_IOGeneral Purpose Digital I/O Pin IOE1
E2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E3VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E4PF3Digital_IOSignal terminal PF3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: ADC.
E9PG5Digital_IOSignal terminal PG5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI.
E10PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: PWM.
E11PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: PWM.
E12PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
F1PH0OSC IN -_ (PH0)Digital_IOSignal terminal PH0OSC IN -_ (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0OSC IN -_ (PH0). Supported peripheral buses: RTC/CLK.
F2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F3PF4Digital_IOSignal terminal PF4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: ADC.
F4PF5Digital_IOSignal terminal PF5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: ADC.
F6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F9PG3Digital_IOSignal terminal PG3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOFMCA13. Supported peripheral buses: SPI.
F10PG4Digital_IOSignal terminal PG4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSIFMCA14. Supported peripheral buses: SPI.
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