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STM32F205RFT6 (LQFP-64(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F205RFT6

STID: C1340245LQFP-64(10x10) · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F205RFT6 (LQFP-64(10x10))1VBAT2PC133PC14/OSC32_I4NC5PH0/OSC_IN (6PH1/OSC_OUT 7NRST8PC09PC110PC211PC312VSSA13VDDA14PA0WKUP - (P15PA116PA217PA318VSS19VDD20PA421PA522PA623PA724PC425PC526PB027PB128PB2/BOOT1(PB29PB1030PB1131VCAP_132VDD64VDD63VSS62PB961PB860BOOT059PB758PB657PB556PB455PB3 (JTDO/TR54PD253PC1252PC1151PC1050PA15(JTDI)49PA14 (JTCKSW48VDD47VCAP_246PA13 (JTMSSW45PA1244PA1143PA1042PA941PA840PC939PC838PC737PC636PB1535PB1434PB1333PB12Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=10.00mm · Pitch e=0.50mmD=10.00mm-9-7-5-3-11357997531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
3PC14/OSC32_IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14/OSC32_IN (PC14) (RTC/CLK)
4NCNCNo Connect (Leave Floating)
5PH0/OSC_IN (PH0)I/OMultiplexed I/O & Peripheral Pin PH0/OSC_IN (PH0) (RTC/CLK)
6PH1/OSC_OUT (PH1)I/OMultiplexed I/O & Peripheral Pin PH1/OSC_OUT (PH1) (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
9PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
10PC2I/OMultiplexed I/O & Peripheral Pin PC2 (SPI, ADC)
11PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI, ADC)
12VSSAGNDGround Reference Pin (VSSA)
13VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
14PA0WKUP - (PA0)I/OMultiplexed I/O & Peripheral Pin PA0WKUP - (PA0) (UART, ADC, PWM)
15PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
16PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
17PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
18VSSGNDGround Reference Pin (VSS)
19VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
20PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
21PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
22PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
23PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
24PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
25PC5I/OMultiplexed I/O & Peripheral Pin PC5 (ADC)
26PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
27PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
28PB2/BOOT1(PB2)I/OMultiplexed I/O & Peripheral Pin PB2/BOOT1(PB2) (General)
29PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, I2C)
30PB11I/OMultiplexed I/O & Peripheral Pin PB11 (I2C, PWM)
31VCAP_1I/OMultiplexed I/O & Peripheral Pin VCAP_1 (General)
32VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
33PB12I/OMultiplexed I/O & Peripheral Pin PB12 (SPI, I2C)
34PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, CAN)
35PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI)
36PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM, RTC/CLK)
37PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
38PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
39PC8I/OMultiplexed I/O & Peripheral Pin PC8 (PWM)
40PC9I/OMultiplexed I/O & Peripheral Pin PC9 (RTC/CLK)
41PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, PWM, RTC/CLK)
42PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C)
43PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
44PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, PWM)
45PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART)
46PA13 (JTMSSWDIO) -I/OMultiplexed I/O & Peripheral Pin PA13 (JTMSSWDIO) - (SWD/JTAG)
47VCAP_2I/OMultiplexed I/O & Peripheral Pin VCAP_2 (General)
48VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
49PA14 (JTCKSWCLK) -I/OMultiplexed I/O & Peripheral Pin PA14 (JTCKSWCLK) - (SWD/JTAG)
50PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (SPI, SWD/JTAG)
51PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
52PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART)
53PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART)
54PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
55PB3 (JTDO/TRACESWO)I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO/TRACESWO) (SPI, PWM, SWD/JTAG)
56PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, PWM, SWD/JTAG)
57PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C)
58PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C, CAN)
59PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
60BOOT0IInput-Only Pin BOOT0 (General)
61PB8I/OMultiplexed I/O & Peripheral Pin PB8 (UART, PWM, CAN)
62PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI, I2C, PWM)
63VSSGNDGround Reference Pin (VSS)
64VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F205RFT6 (ST · LQFP-64(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F205RFT6 (LQFP-64(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F205RFT6 (LQFP-64(10x10)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F205RFT6 (LQFP-64(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F205RFT6 (LQFP-64(10x10)) - 4. Package Dimensions (D×E×A)
LQFP-64(10x10) · 10.00×10.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F205RFT6 (LQFP-64(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F205RFT6 (LQFP-64(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for STM32F207 / STM32F205
P41 · p41_fig01EXACT PACKAGE
STM32F205RFT6 (LQFP-64(10x10)) — Figure 10. STM32F20x LQFP64 pinout
Figure 10. STM32F20x LQFP64 pinout
P148 · p148_fig01EXACT PACKAGE
STM32F205RFT6 (LQFP-64(10x10)) — Figure 77. LQFP64 outline
Figure 77. LQFP64 outline
P149 · p149_fig01EXACT PACKAGE
STM32F205RFT6 (LQFP-64(10x10)) — Figure 78. LQFP64 recommended footprint
Figure 78. LQFP64 recommended footprint
P1 · p01_fig01881×566px
STM32F205RFT6 (LQFP-64(10x10)) —   Up to 140 I/O ports with interrupt capability: - Up to 136 fast I/Os up to 60 MHz - Up to 138 5 V-tolerant I/Os
  Up to 140 I/O ports with interrupt capability: - Up to 136 fast I/Os up to 60 MHz - Up to 138 5 V-tolerant I/Os
P41 · p41_fig021546×1321px
STM32F205RFT6 (LQFP-64(10x10)) — Figure 11. STM32F20x WLCSP64+2 ballout 1 2 3 8
Figure 11. STM32F20x WLCSP64+2 ballout 1 2 3 8
P41 · p41_fig01P41
STM32F205RFT6 (LQFP-64(10x10)) — Datasheet Page 41 (p41_fig01)
Datasheet Page 41 (p41_fig01)
P68 · p68_fig011751×1623px
STM32F205RFT6 (LQFP-64(10x10)) — Figure 19. Power supply scheme VBAT
Figure 19. Power supply scheme VBAT
P68 · p68_fig01P68
STM32F205RFT6 (LQFP-64(10x10)) — Datasheet Page 68 (p68_fig01)
Datasheet Page 68 (p68_fig01)
P90 · p90_fig011546×484px
STM32F205RFT6 (LQFP-64(10x10)) — Figure 32. Typical application with an 8 MHz crystal
Figure 32. Typical application with an 8 MHz crystal
P91 · p91_fig011751×593px
STM32F205RFT6 (LQFP-64(10x10)) — Figure 33. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors
Figure 33. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors
P123 · p123_fig011546×1171px
STM32F205RFT6 (LQFP-64(10x10)) — Figure 52. ADC accuracy characteristics VREF+
Figure 52. ADC accuracy characteristics VREF+
P123 · p123_fig021546×571px
STM32F205RFT6 (LQFP-64(10x10)) — Figure 53. Typical connection diagram using the ADC
Figure 53. Typical connection diagram using the ADC
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (STM32F205RFT6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F205RFT6 (LQFP-64(10x10)) is a 64-pin embedded microcontroller unit (mcu) featuring a 10.00 × 10.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, CAN, DAC, RTC/CLK, SPI, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
120 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
49 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-64(10x10))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, CAN, DAC, RTC/CLK, SPI, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2/BOOT1(PB2), BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-64(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.20 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-64(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F205RFT6 (LQFP-64(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F205RFT6 (LQFP-64(10x10))?

Manufactured by ST, the STM32F205RFT6 is housed in a LQFP-64(10x10) package with 64 pins and a 0.50 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (PC14/OSC32_IN (PC14): Multiplexed I/O & Peripheral Pin PC14/OSC32_IN (PC14) (RTC/CLK)), 4 (NC: No Connect (Leave Floating)), 5 (PH0/OSC_IN (PH0): Multiplexed I/O & Peripheral Pin PH0/OSC_IN (PH0) (RTC/CLK)), 6 (PH1/OSC_OUT (PH1): Multiplexed I/O & Peripheral Pin PH1/OSC_OUT (PH1) (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32F205RFT6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F205RFT6 (LQFP-64(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F205RFT6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F205RFT6 (ST, LQFP-64(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & STM32F207 / STM32F205 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
3PC14/OSC32_IN (PC14)Digital_IOSignal terminal PC14/OSC32_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14/OSC32_IN (PC14). Supported peripheral buses: RTC/CLK.
4NCNo_ConnectNo Connect (Leave Floating)
5PH0/OSC_IN (PH0)Digital_IOSignal terminal PH0/OSC_IN (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0/OSC_IN (PH0). Supported peripheral buses: RTC/CLK.
6PH1/OSC_OUT (PH1)Digital_IOSignal terminal PH1/OSC_OUT (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1/OSC_OUT (PH1). Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
9PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
10PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, ADC.
11PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSII2S2SD. Supported peripheral buses: SPI, ADC.
12VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
13VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
14PA0WKUP - (PA0)Digital_IOSignal terminal PA0WKUP - (PA0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0WKUP - (PA0). Supported peripheral buses: UART, ADC, PWM.
15PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
16PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
17PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
18VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
19VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
20PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSSPI3NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
21PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC, PWM.
22PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOTIM8BKIN. Supported peripheral buses: SPI, ADC, PWM.
23PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSITIM8CH1N. Supported peripheral buses: SPI, ADC, PWM.
24PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
25PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC.
26PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
27PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
28PB2/BOOT1(PB2)Digital_IOSignal terminal PB2/BOOT1(PB2) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2/BOOT1(PB2). Supported peripheral buses: General.
29PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKI2S2SCK. Supported peripheral buses: SPI, I2C.
30PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: I2C, PWM.
31VCAP_1Digital_IOSignal terminal VCAP_1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_1. Supported peripheral buses: General.
32VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
33PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSI2S2WS. Supported peripheral buses: SPI, I2C.
34PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKI2S2SCK. Supported peripheral buses: UART, SPI, CAN.
35PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOTIM1CH2N. Supported peripheral buses: UART, SPI.
36PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSII2S2SD. Supported peripheral buses: SPI, PWM, RTC/CLK.
37PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
38PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
39PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: PWM.
40PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: RTC/CLK.
41PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, PWM, RTC/CLK.
42PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, I2C.
43PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
44PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: UART, PWM.
45PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART.
46PA13 (JTMSSWDIO) -Digital_IOSignal terminal PA13 (JTMSSWDIO) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMSSWDIO) -. Supported peripheral buses: SWD/JTAG.
47VCAP_2Digital_IOSignal terminal VCAP_2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_2. Supported peripheral buses: General.
48VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
49PA14 (JTCKSWCLK) -Digital_IOSignal terminal PA14 (JTCKSWCLK) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (JTCKSWCLK) -. Supported peripheral buses: SWD/JTAG.
50PA15(JTDI)Digital_IOSignal terminal PA15(JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_NSS, SPI1_NSSEVENTOUT. Supported peripheral buses: SPI, SWD/JTAG.
51PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCKI2S3SCK. Supported peripheral buses: UART, SPI.
52PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: UART.
53PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: UART.
54PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
55PB3 (JTDO/TRACESWO)Digital_IOSignal terminal PB3 (JTDO/TRACESWO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCKI2S3SCK. Supported peripheral buses: SPI, PWM, SWD/JTAG.
56PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: SPI, PWM, SWD/JTAG.
57PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSISPI3MOSI. Supported peripheral buses: SPI, I2C.
58PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: I2C, CAN.
59PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
60BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
61PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: UART, PWM, CAN.
62PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSI2S2WS. Supported peripheral buses: SPI, I2C, PWM.
63VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
64VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
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