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STM32F103RBH7 (BGA-64) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F103RBH7

STBGA-64 · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F103RBH7 (BGA-64)A1PC14 -OSC32 A2PC13TAMPER -A3PB9A4PB4A5PB3A6PA15A7PA14A8PA13B1PC15 - OSC32B2VBATB3PB8B4BOOT0B5PD2B6PC11B7PC10B8PA12C1PD0C2VSS_4C3PB7C4PB5C5PC12C6PA10C7PA9C8PA11D1PD1D2VDD_4D3PB6D4VSS_3D5VSS_2D6VSS_1D7PA8D8PC9H8PB12H7PB11H6PC5H5PC4H4PA7H3PA4H2PA1H1VDDAG8PB13G7PB10G6PB2G5PB1G4PA6G3PA3G2PA0 WKUP -G1VREF+F8PB14F7PB15F6PC6F5PB0F4PA5F3PA2F2PC2F1VSSAE8PC8E7PC7E6VDD_1E5VDD_2E4VDD_3E3PC0E2PC1E1NRSTGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1A2B2C2D2E2F2G2H2A3B3C3D3E3F3G3H3A4B4C4D4E4F4G4H4A5B5C5D5E5F5G5H5A6B6C6D6E6F6G6H6A7B7C7D7E7F7G7H7A8B8C8D8E8F8G8H8E=5.00mm · Pitch e=0.50mmD=5.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PC14 -OSC32 IN(5)_I/OMultiplexed I/O & Peripheral Pin PC14 -OSC32 IN(5)_ (RTC/CLK)
A2PC13TAMPER - - RTCI/OMultiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)
A3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
A4PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
A5PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SWD/JTAG)
A6PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SWD/JTAG)
A7PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
A8PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
B1PC15 - OSC32 OUT(5)_I/OMultiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(5)_ (RTC/CLK)
B2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B3PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
B4BOOT0IInput-Only Pin BOOT0 (General)
B5PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
B6PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
B7PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
B8PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, CAN)
C1PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
C2VSS_4GNDGround Reference Pin (VSS_4)
C3PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
C4PB5I/OMultiplexed I/O & Peripheral Pin PB5 (I2C)
C5PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
C6PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
C7PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART)
C8PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, CAN)
D1PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
D2VDD_4PowerPower Supply Input (VDD_4 — 3.3V VDD (Max 4.0V))
D3PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C)
D4VSS_3GNDGround Reference Pin (VSS_3)
D5VSS_2GNDGround Reference Pin (VSS_2)
D6VSS_1GNDGround Reference Pin (VSS_1)
D7PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
D8PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E1NRSTISystem Enable & Hardware Reset (NRST)
E2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
E3PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
E4VDD_3PowerPower Supply Input (VDD_3 — 3.3V VDD (Max 4.0V))
E5VDD_2PowerPower Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
E6VDD_1PowerPower Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
E7PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
E8PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
F1VSSAGNDGround Reference Pin (VSSA)
F2PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
F3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC)
F4PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
F5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC)
F6PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
F7PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI)
F8PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI)
G1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
G2PA0 WKUP -I/OMultiplexed I/O & Peripheral Pin PA0 WKUP - (UART, ADC, PWM)
G3PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC)
G4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
G5PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC)
G6PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
G7PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, I2C)
G8PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI)
H1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
H2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
H3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, ADC)
H4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
H5PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
H6PC5I/OMultiplexed I/O & Peripheral Pin PC5 (ADC)
H7PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C)
H8PB12I/OMultiplexed I/O & Peripheral Pin PB12 (SPI, I2C)
PIN A1 PC14 -OSC32 IN(5)_
I/O
Multiplexed I/O & Peripheral Pin PC14 -OSC32 IN(5)_ (RTC/CLK)
Design note: PC14(6) | Alt: OSC32_IN
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F103RBH7 (ST · BGA-64)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F103RBH7 (BGA-64) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F103RBH7 (BGA-64) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F103RBH7 (BGA-64) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F103RBH7 (BGA-64) - 4. Package Dimensions (D×E×A)
BGA-64 · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F103RBH7 (BGA-64) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F103RBH7 (BGA-64) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for STM32F103
P97 · p97_fig01EXACT PACKAGE
STM32F103RBH7 (BGA-64) — Figure 57. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
Figure 57. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
P99 · p99_fig01EXACT PACKAGE
STM32F103RBH7 (BGA-64) — Figure 59. TFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid
Figure 59. TFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid
P100 · p100_fig01EXACT PACKAGE
STM32F103RBH7 (BGA-64) — Figure 60. TFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid
Figure 60. TFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid
P1 · p01_fig01881×629px
STM32F103RBH7 (BGA-64) — STM32F103x8 STM32F103xB Medium-density performance line ARM®-based 32-bit MCU with 64
STM32F103x8 STM32F103xB Medium-density performance line ARM®-based 32-bit MCU with 64
P21 · p21_fig011751×1835px
STM32F103RBH7 (BGA-64) — Figure 3. STM32F103xx performance line LFBGA100 ballout
Figure 3. STM32F103xx performance line LFBGA100 ballout
P23 · p23_fig011751×1734px
STM32F103RBH7 (BGA-64) — Figure 5. STM32F103xx performance line UFBGA100 pinout
Figure 5. STM32F103xx performance line UFBGA100 pinout
P54 · p54_fig011546×513px
STM32F103RBH7 (BGA-64) — Figure 24. Typical application with an 8 MHz crystal
Figure 24. Typical application with an 8 MHz crystal
P55 · p55_fig011751×683px
STM32F103RBH7 (BGA-64) — Figure 25. Typical application with a 32.768 kHz crystal
Figure 25. Typical application with a 32.768 kHz crystal
P88 · p88_fig011543×398px
STM32F103RBH7 (BGA-64) — Figure 48. LFBGA100 - 100-ball low-profile fine pitch ball grid array, 10 x 10 mm,
Figure 48. LFBGA100 - 100-ball low-profile fine pitch ball grid array, 10 x 10 mm,
P88 · p88_fig021560×1117px
STM32F103RBH7 (BGA-64) — Figure 48. LFBGA100 - 100-ball low-profile fine pitch ball grid array, 10 x 10 mm,
Figure 48. LFBGA100 - 100-ball low-profile fine pitch ball grid array, 10 x 10 mm,
P114 · p114_fig011543×2321px
STM32F103RBH7 (BGA-64) — Revision history STM32F103x8, STM32F103xB
Revision history STM32F103x8, STM32F103xB
P1 · p01_fig02All Packages in PDF
STM32F103RBH7 (BGA-64) — • Packages are ECOPACK®
• Packages are ECOPACK®

Technical Specifications & Part Details (STM32F103RBH7)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F103RBH7 (BGA-64) is a 64-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 1.20 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
72 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 1.20 mm (A1=0.30 mm)
Package family: BGA (BGA-64)
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PB2): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (BGA-64)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.50mm
Pad Size (W × L)Level B
0.22 × 0.22 mm
Pins / Total PadsTopology
64P / 64Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2, C3
BOM
3× 100nF (0.1µF) 50V X7R
0402 / 0603
Digital supply decoupling caps for VDD_1..3 (Pins 24, 36, 48) — place < 1.5mm from each VDD pin.
C4
BOM
4.7µF ~ 10µF 10V X5R
0603 / 0805
Bulk decoupling capacitor for main VDD rail — place near 3.3V power entry to the MCU.
C5, C6 + FB1
BOM
100nF + 1µF + Ferrite 600Ω@100MHz
0402 / 0603
Analog rail filter for VDDA/VSSA (Pins 8, 9) 12-bit ADC — isolate digital switching noise.
Y1 + C7, C8
BOM
8MHz Crystal (CL=12pF) + 2× 18pF NP0
SMD-3225 + 0402
Main HSE oscillator crystal (Pin 5 PD0, Pin 6 PD1) — route matched traces < 4mm with GND guard ring.
STM32F103CBT6
STMicroelectronics
100% Drop-in (128KB Flash Upgrade)100% Drop-in (128KB Flash Upgrade) — identical LQFP-48 pinout with doubled Flash capacity.
GD32F103C8T6
GigaDevice
Pin-to-Pin LQFP-48 (108MHz)Pin-to-Pin LQFP-48 (108MHz) — higher core clock; verify Flash wait-states & USB timing.
APM32F103C8T6
Geehy
Pin-to-Pin LQFP-48 (96MHz)Pin-to-Pin LQFP-48 (96MHz) — direct hardware replacement, register-compatible with STM32F1.

Technical Frequently Asked Questions (FAQ) — STM32F103RBH7 (BGA-64)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F103RBH7 (BGA-64)?

Manufactured by ST, the STM32F103RBH7 is housed in a BGA-64 package with 64 pins and a 0.50 mm lead pitch. Key pins include: A1 (PC14 -OSC32 IN(5)_: Multiplexed I/O & Peripheral Pin PC14 -OSC32 IN(5)_ (RTC/CLK)), A2 (PC13TAMPER - - RTC: Multiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)), A3 (PB9: Multiplexed I/O & Peripheral Pin PB9 (General)), A4 (PB4: Multiplexed I/O & Peripheral Pin PB4 (General)), A5 (PB3: Multiplexed I/O & Peripheral Pin PB3 (SWD/JTAG)), A6 (PA15: Multiplexed I/O & Peripheral Pin PA15 (SWD/JTAG)).

What are the IPC-7351B PCB Footprint dimensions for STM32F103RBH7?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F103RBH7 (BGA-64) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F103RBH7?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F103RBH7 (ST, BGA-64) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & STM32F103 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PC14 -OSC32 IN(5)_Digital_IOSignal terminal PC14 -OSC32 IN(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14 -OSC32 IN(5)_. Supported peripheral buses: RTC/CLK.
A2PC13TAMPER - - RTCDigital_IOSignal terminal PC13TAMPER - - RTC (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13TAMPER - - RTC. Supported peripheral buses: RTC/CLK.
A3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
A4PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
A5PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: SWD/JTAG.
A6PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: SWD/JTAG.
A7PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
A8PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
B1PC15 - OSC32 OUT(5)_Digital_IOSignal terminal PC15 - OSC32 OUT(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15 - OSC32 OUT(5)_. Supported peripheral buses: RTC/CLK.
B2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B3PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
B4BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
B5PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
B6PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
B7PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
B8PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: USB, UART, CAN.
C1PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
C2VSS_4GND0V electrical ground return terminal (VSS_4) for internal core logic, I/O drivers, and analog sub-blocks.
C3PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
C4PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SMBAL. Supported peripheral buses: I2C.
C5PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
C6PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
C7PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART.
C8PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: USB, UART, CAN.
D1PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
D2VDD_4Power_InPrimary positive power supply input (VDD_4) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D3PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
D4VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
D5VSS_2GND0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks.
D6VSS_1GND0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks.
D7PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
D8PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E1NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E2PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
E3PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
E4VDD_3Power_InPrimary positive power supply input (VDD_3) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E5VDD_2Power_InPrimary positive power supply input (VDD_2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E6VDD_1Power_InPrimary positive power supply input (VDD_1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E7PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
E8PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
F1VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
F2PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC.
F3PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC.
F4PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC.
F5PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC.
F6PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
F7PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI.
F8PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI.
G1VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
G2PA0 WKUP -Digital_IOSignal terminal PA0 WKUP - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0 WKUP -. Supported peripheral buses: UART, ADC, PWM.
G3PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC.
G4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC.
G5PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC.
G6PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
G7PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: UART, I2C.
G8PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI.
H1VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
H2PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC.
H3PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI, ADC.
H4PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC.
H5PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
H6PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC.
H7PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: UART, I2C.
H8PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_NSS, I2C2_SMBAL. Supported peripheral buses: SPI, I2C.
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