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STM32F103T8U7 (VFQFPN36(6x6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F103T8U7

STID: C1337356VFQFPN36(6x6) · 37 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F103T8U7 (VFQFPN36(6x6))1VDD_32PD03PD14NRST5VSSA6VDDA7PA0 WKUP -8PA19PA210PA311PA412PA513PA614PA715PB016PB117PB218VSS_119VDD_137EP36VSS_335BOOT034PB733PB632PB531PB430PB329PA1528PA1427VDD_226VSS_225PA1324PA1223PA1122PA1021PA920PA8Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.830.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637E=6.00mm · Pitch e=0.50mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (37/37)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDD_3PowerPower Supply Input (VDD_3 — 3.3V VDD (Max 4.0V))
2PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
3PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
4NRSTISystem Enable & Hardware Reset (NRST)
5VSSAGNDGround Reference Pin (VSSA)
6VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
7PA0 WKUP -I/OMultiplexed I/O & Peripheral Pin PA0 WKUP - (UART, ADC, PWM)
8PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
9PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC)
10PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC)
11PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, ADC)
12PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
13PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
14PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
15PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC)
16PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC)
17PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
18VSS_1GNDGround Reference Pin (VSS_1)
19VDD_1PowerPower Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
20PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
21PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART)
22PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
23PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, CAN)
24PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, CAN)
25PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
26VSS_2GNDGround Reference Pin (VSS_2)
27VDD_2PowerPower Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
28PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
29PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SWD/JTAG)
30PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SWD/JTAG)
31PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
32PB5I/OMultiplexed I/O & Peripheral Pin PB5 (I2C)
33PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C)
34PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
35BOOT0IInput-Only Pin BOOT0 (General)
36VSS_3GNDGround Reference Pin (VSS_3)
37EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 VDD_3
Power
Power Supply Input (VDD_3 — 3.3V VDD (Max 4.0V))
Design note: VDD_3
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F103T8U7 (ST · VFQFPN36(6x6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F103T8U7 (VFQFPN36(6x6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F103T8U7 (VFQFPN36(6x6)) - 2. Standard Pinout (Top View)
True package pinout (37 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F103T8U7 (VFQFPN36(6x6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F103T8U7 (VFQFPN36(6x6)) - 4. Package Dimensions (D×E×A)
VFQFPN36(6x6) · 6.00×6.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F103T8U7 (VFQFPN36(6x6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (37 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F103T8U7 (VFQFPN36(6x6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for STM32F103
P26 · p26_fig01EXACT PACKAGE
STM32F103T8U7 (VFQFPN36(6x6)) — Figure 8. STM32F103xx performance line LQFP48 pinout
Figure 8. STM32F103xx performance line LQFP48 pinout
P26 · p26_fig02EXACT PACKAGE
STM32F103T8U7 (VFQFPN36(6x6)) — Figure 9. STM32F103xx performance line UFQFPN48 pinout
Figure 9. STM32F103xx performance line UFQFPN48 pinout
P27 · p27_fig01EXACT PACKAGE
STM32F103T8U7 (VFQFPN36(6x6)) — Figure 10. STM32F103xx performance line VFQFPN36 pinout
Figure 10. STM32F103xx performance line VFQFPN36 pinout
P82 · p82_fig01EXACT PACKAGE
STM32F103T8U7 (VFQFPN36(6x6)) — Figure 42. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad
Figure 42. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad
P84 · p84_fig01EXACT PACKAGE
STM32F103T8U7 (VFQFPN36(6x6)) — Figure 44. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
Figure 44. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
P84 · p84_fig02EXACT PACKAGE
STM32F103T8U7 (VFQFPN36(6x6)) — 84/117 DocID13587 Rev 17
84/117 DocID13587 Rev 17
P85 · p85_fig01EXACT PACKAGE
STM32F103T8U7 (VFQFPN36(6x6)) — Figure 45. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
Figure 45. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
P1 · p01_fig01881×629px
STM32F103T8U7 (VFQFPN36(6x6)) — STM32F103x8 STM32F103xB Medium-density performance line ARM®-based 32-bit MCU with 64
STM32F103x8 STM32F103xB Medium-density performance line ARM®-based 32-bit MCU with 64
P27 · p27_fig01P27
STM32F103T8U7 (VFQFPN36(6x6)) — Datasheet Page 27 (p27_fig01)
Datasheet Page 27 (p27_fig01)
P54 · p54_fig011546×513px
STM32F103T8U7 (VFQFPN36(6x6)) — Figure 24. Typical application with an 8 MHz crystal
Figure 24. Typical application with an 8 MHz crystal
P55 · p55_fig011751×683px
STM32F103T8U7 (VFQFPN36(6x6)) — Figure 25. Typical application with a 32.768 kHz crystal
Figure 25. Typical application with a 32.768 kHz crystal
P55 · p55_fig01P55
STM32F103T8U7 (VFQFPN36(6x6)) — Datasheet Page 55 (p55_fig01)
Datasheet Page 55 (p55_fig01)
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (STM32F103T8U7)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F103T8U7 (VFQFPN36(6x6)) is a 36-pin embedded microcontroller unit (mcu) featuring a 6.00 × 6.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
72 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 0.90 mm (A1=0.04 mm)
Package family: QFN (VFQFPN36(6x6))
Pin Count & Lead PitchN / e
36 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol37 auto-grouped pins
OK
IPC-7351B Land Pattern37 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.70×3.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (VFQFPN36(6x6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.50mm
Pad Size (W × L)Level B
0.27 × 0.95 mm
Pins / Total PadsTopology
37P / 37Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2, C3
BOM
3× 100nF (0.1µF) 50V X7R
0402 / 0603
Digital supply decoupling caps for VDD_1..3 (Pins 24, 36, 48) — place < 1.5mm from each VDD pin.
C4
BOM
4.7µF ~ 10µF 10V X5R
0603 / 0805
Bulk decoupling capacitor for main VDD rail — place near 3.3V power entry to the MCU.
C5, C6 + FB1
BOM
100nF + 1µF + Ferrite 600Ω@100MHz
0402 / 0603
Analog rail filter for VDDA/VSSA (Pins 8, 9) 12-bit ADC — isolate digital switching noise.
Y1 + C7, C8
BOM
8MHz Crystal (CL=12pF) + 2× 18pF NP0
SMD-3225 + 0402
Main HSE oscillator crystal (Pin 5 PD0, Pin 6 PD1) — route matched traces < 4mm with GND guard ring.
STM32F103CBT6
STMicroelectronics
100% Drop-in100% Drop-in (128KB Flash Upgrade) — identical LQFP-48 pinout with doubled Flash capacity.
GD32F103C8T6
GigaDevice
Pin-to-Pin LQFP-48 (108MHz)Pin-to-Pin LQFP-48 (108MHz) — higher core clock; verify Flash wait-states & USB timing.
APM32F103C8T6
Geehy
Pin-to-Pin LQFP-48 (96MHz)Pin-to-Pin LQFP-48 (96MHz) — direct hardware replacement, register-compatible with STM32F1.

Technical Frequently Asked Questions (FAQ) — STM32F103T8U7 (VFQFPN36(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F103T8U7 (VFQFPN36(6x6))?

Manufactured by ST, the STM32F103T8U7 is housed in a VFQFPN36(6x6) package with 37 pins and a 0.50 mm lead pitch. Key pins include: 1 (VDD_3: Power Supply Input (VDD_3 — 3.3V VDD (Max 4.0V))), 2 (PD0: Multiplexed I/O & Peripheral Pin PD0 (General)), 3 (PD1: Multiplexed I/O & Peripheral Pin PD1 (General)), 4 (NRST: System Enable & Hardware Reset (NRST)), 5 (VSSA: Ground Reference Pin (VSSA)), 6 (VDDA: Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))).

What are the IPC-7351B PCB Footprint dimensions for STM32F103T8U7?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F103T8U7 (VFQFPN36(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.50 mm, and 37 copper pads plus a central exposed thermal pad (EPAD) of 3.70 × 3.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F103T8U7?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F103T8U7 (ST, VFQFPN36(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (37 pins) & STM32F103 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDD_3Power_InPrimary positive power supply input (VDD_3) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
3PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
4NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
5VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
6VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
7PA0 WKUP -Digital_IOSignal terminal PA0 WKUP - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0 WKUP -. Supported peripheral buses: UART, ADC, PWM.
8PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC.
9PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC.
10PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC.
11PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI, ADC.
12PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC.
13PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC.
14PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC.
15PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC.
16PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC.
17PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
18VSS_1GND0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks.
19VDD_1Power_InPrimary positive power supply input (VDD_1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
20PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
21PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART.
22PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
23PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: USB, UART, CAN.
24PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: USB, UART, CAN.
25PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
26VSS_2GND0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks.
27VDD_2Power_InPrimary positive power supply input (VDD_2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
28PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
29PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: SWD/JTAG.
30PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: SWD/JTAG.
31PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
32PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SMBAL. Supported peripheral buses: I2C.
33PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
34PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
35BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
36VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
37EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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