STM32F722VET6 (LQFP-100(14x14)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of STM32F722VET6 (LQFP-100(14x14))?

Manufactured by ST, the STM32F722VET6 is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (PH0OSC IN -_: Multiplexed I/O & Peripheral Pin PH0OSC IN -_ (RTC/CLK)), 6 (PH1OSC OUT -_: Multiplexed I/O & Peripheral Pin PH1OSC OUT -_ (RTC/CLK)).

Q: What are the IPC-7351B PCB Footprint dimensions for STM32F722VET6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F722VET6 (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F722VET6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F722VET6 (ST, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 14.00mm × 14.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	VBAT	Power	Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))
2	PC13	I/O	Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
3	3V3	Power	3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4	NC	NC	No Connect (Leave Floating)
5	PH0OSC IN -_	I/O	Multiplexed I/O & Peripheral Pin PH0OSC IN -_ (RTC/CLK)
6	PH1OSC OUT -_	I/O	Multiplexed I/O & Peripheral Pin PH1OSC OUT -_ (RTC/CLK)
7	NRST	I	System Enable & Hardware Reset (NRST)
8	PC0	I/O	Multiplexed I/O & Peripheral Pin PC0 (ADC)
9	PC1	I/O	Multiplexed I/O & Peripheral Pin PC1 (SPI, I2C, ADC, RTC/CLK)
10	PC2	I/O	Multiplexed I/O & Peripheral Pin PC2 (SPI, ADC)
11	PC3	I/O	Multiplexed I/O & Peripheral Pin PC3 (SPI, ADC)
12	VSSA	GND	Ground Reference Pin (VSSA)
13	VREF+	Analog	Multiplexed I/O & Peripheral Pin VREF+ (General)
14	PA0WKUP -	I/O	Multiplexed I/O & Peripheral Pin PA0WKUP - (UART, ADC, PWM)
15	PA1	I/O	Multiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
16	PA2	I/O	Multiplexed I/O & Peripheral Pin PA2 (SPI, ADC, PWM)
17	PA3	I/O	Multiplexed I/O & Peripheral Pin PA3 (ADC, PWM)
18	VSS	GND	Ground Reference Pin (VSS)
19	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
20	PA4	I/O	Multiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
21	PA5	I/O	Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
22	PA6	I/O	Multiplexed I/O & Peripheral Pin PA6 (ADC)
23	PA7	I/O	Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
24	PC4	I/O	Multiplexed I/O & Peripheral Pin PC4 (ADC)
25	PB0	I/O	Multiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
26	PB1	I/O	Multiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
27	PB2	I/O	Multiplexed I/O & Peripheral Pin PB2 (SPI, I2C)
28	PB10	I/O	Multiplexed I/O & Peripheral Pin PB10 (UART, SPI, PWM)
29	PB11	I/O	Multiplexed I/O & Peripheral Pin PB11 (UART, PWM)
30	VCAP_1	I/O	Multiplexed I/O & Peripheral Pin VCAP_1 (General)
31	VSS	GND	Ground Reference Pin (VSS)
32	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
33	PB12	I/O	Multiplexed I/O & Peripheral Pin PB12 (UART, SPI)
34	PB13	I/O	Multiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
35	PB14	I/O	Multiplexed I/O & Peripheral Pin PB14 (SPI, PWM)
36	PB15	I/O	Multiplexed I/O & Peripheral Pin PB15 (SPI, PWM, RTC/CLK)
37	PC6	I/O	Multiplexed I/O & Peripheral Pin PC6 (PWM)
38	PC7	I/O	Multiplexed I/O & Peripheral Pin PC7 (PWM)
39	PC8	I/O	Multiplexed I/O & Peripheral Pin PC8 (UART, PWM)
40	PC9	I/O	Multiplexed I/O & Peripheral Pin PC9 (UART, I2C, RTC/CLK)
41	PA8	I/O	Multiplexed I/O & Peripheral Pin PA8 (I2C, RTC/CLK)
42	PA9	I/O	Multiplexed I/O & Peripheral Pin PA9 (UART, SPI, PWM)
43	PA10	I/O	Multiplexed I/O & Peripheral Pin PA10 (PWM)
44	PA11	I/O	Multiplexed I/O & Peripheral Pin PA11 (PWM, CAN)
45	PA12	I/O	Multiplexed I/O & Peripheral Pin PA12 (General)
46	PA13(JTMS - SWDIO)	I/O	Multiplexed I/O & Peripheral Pin PA13(JTMS - SWDIO) (SWD/JTAG)
47	VSS	GND	Ground Reference Pin (VSS)
48	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
49	PA14(JTCK - SWCLK)	I/O	Multiplexed I/O & Peripheral Pin PA14(JTCK - SWCLK) (SWD/JTAG)
50	PA15(JTDI)	I/O	Multiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG)
51	PC10	I/O	Multiplexed I/O & Peripheral Pin PC10 (UART, SPI)
52	PC11	I/O	Multiplexed I/O & Peripheral Pin PC11 (UART, SPI)
53	PC12	I/O	Multiplexed I/O & Peripheral Pin PC12 (UART, SPI)
54	PD2	I/O	Multiplexed I/O & Peripheral Pin PD2 (UART)
55	PD8	I/O	Multiplexed I/O & Peripheral Pin PD8 (General)
56	PD9	I/O	Multiplexed I/O & Peripheral Pin PD9 (General)
57	PD10	I/O	Multiplexed I/O & Peripheral Pin PD10 (General)
58	PD11	I/O	Multiplexed I/O & Peripheral Pin PD11 (UART, I2C)
59	PD12	I/O	Multiplexed I/O & Peripheral Pin PD12 (UART, PWM)
60	PD13	I/O	Multiplexed I/O & Peripheral Pin PD13 (SPI, PWM)
61	PD14	I/O	Multiplexed I/O & Peripheral Pin PD14 (PWM)
62	PD15	I/O	Multiplexed I/O & Peripheral Pin PD15 (PWM)
63	PC6	I/O	Multiplexed I/O & Peripheral Pin PC6 (General)
64	PC7	I/O	Multiplexed I/O & Peripheral Pin PC7 (General)
65	PC8	I/O	Multiplexed I/O & Peripheral Pin PC8 (General)
66	PC9	I/O	Multiplexed I/O & Peripheral Pin PC9 (General)
67	PA8	I/O	Multiplexed I/O & Peripheral Pin PA8 (General)
68	PA9	I/O	Multiplexed I/O & Peripheral Pin PA9 (General)
69	PA10	I/O	Multiplexed I/O & Peripheral Pin PA10 (General)
70	PA11	I/O	Multiplexed I/O & Peripheral Pin PA11 (General)
71	PA12	I/O	Multiplexed I/O & Peripheral Pin PA12 (General)
72	PA13	I/O	Multiplexed I/O & Peripheral Pin PA13 (General)
73	VCAP2	I/O	Multiplexed I/O & Peripheral Pin VCAP2 (General)
74	VSS	GND	Ground Reference Pin (VSS)
75	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
76	PA14	I/O	Multiplexed I/O & Peripheral Pin PA14 (General)
77	PA15	I/O	Multiplexed I/O & Peripheral Pin PA15 (General)
78	PC10	I/O	Multiplexed I/O & Peripheral Pin PC10 (General)
79	PC11	I/O	Multiplexed I/O & Peripheral Pin PC11 (General)
80	PC12	I/O	Multiplexed I/O & Peripheral Pin PC12 (General)
81	PD0	I/O	Multiplexed I/O & Peripheral Pin PD0 (General)
82	PD1	I/O	Multiplexed I/O & Peripheral Pin PD1 (General)
83	PD2	I/O	Multiplexed I/O & Peripheral Pin PD2 (General)
84	PD3	I/O	Multiplexed I/O & Peripheral Pin PD3 (General)
85	PD4	I/O	Multiplexed I/O & Peripheral Pin PD4 (General)
86	PD5	I/O	Multiplexed I/O & Peripheral Pin PD5 (General)
87	PD6	I/O	Multiplexed I/O & Peripheral Pin PD6 (General)
88	PD7	I/O	Multiplexed I/O & Peripheral Pin PD7 (General)
89	PB3	I/O	Multiplexed I/O & Peripheral Pin PB3 (General)
90	PB4	I/O	Multiplexed I/O & Peripheral Pin PB4 (General)
91	PB5	I/O	Multiplexed I/O & Peripheral Pin PB5 (General)
92	PB6	I/O	Multiplexed I/O & Peripheral Pin PB6 (General)
93	PB7	I/O	Multiplexed I/O & Peripheral Pin PB7 (General)
94	BOOT0	I	Input-Only Pin BOOT0 (General)
95	PB8	I/O	Multiplexed I/O & Peripheral Pin PB8 (General)
96	PB9	I/O	Multiplexed I/O & Peripheral Pin PB9 (General)
97	PE0	I/O	Multiplexed I/O & Peripheral Pin PE0 (General)
98	PE1	I/O	Multiplexed I/O & Peripheral Pin PE1 (General)
99	VSS	GND	Ground Reference Pin (VSS)
100	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))

PIN 1 VBAT

Power

Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))

Design note: Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

STM32F722VET6 (LQFP-100(14x14)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

STM32F722VET6 (LQFP-100(14x14)) - 2. Standard Pinout (Top View)

True package pinout (100 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

STM32F722VET6 (LQFP-100(14x14)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

STM32F722VET6 (LQFP-100(14x14)) - 4. Package Dimensions (D×E×A)

LQFP-100(14x14) · 14.00×14.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

STM32F722VET6 (LQFP-100(14x14)) - 5. Recommended Land Pattern

IPC-7351B Footprint (100 Pads)Expand ›

6. Application SchematicSCHEMATIC

STM32F722VET6 (LQFP-100(14x14)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)

Showing 1–12 of 14 uncropped original figures for STM32F722 / STM32F723

P49 · p49_fig01EXACT PACKAGE

Figure 15. STM32F722xx LQFP100 pinout

P205 · p205_fig01EXACT PACKAGE

Figure 82. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline 3%!4).'0,!.%

P206 · p206_fig01EXACT PACKAGE

Figure 83. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package

P1 · p01_fig01881×615px

• 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode

P49 · p49_fig01P49

Datasheet Page 49 (p49_fig01)

P103 · p103_fig011546×1696px

Figure 27. STM32F722xx power supply scheme

P103 · p103_fig01P103

Datasheet Page 103 (p103_fig01)

P134 · p134_fig011546×487px

Figure 38. Typical application with an 8 MHz crystal

P135 · p135_fig011546×516px

Figure 39. Typical application with a 32.768 kHz crystal

P159 · p159_fig011546×1229px

Figure 47. ADC accuracy characteristics

P159 · p159_fig021546×604px

Figure 48. Typical connection diagram using the ADC

P205 · p205_fig01P205

Datasheet Page 205 (p205_fig01)

Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (STM32F722VET6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Embedded Microcontroller Unit (MCU)

Detailed Overview:STM32F722VET6 (LQFP-100(14x14)) is a 100-pin embedded microcontroller unit (mcu) featuring a 14.00 × 14.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.7 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, CAN, DAC, RTC/CLK, SWD/JTAG, UART interfaces.

Operating Supply VoltageV_CC / V_DD

1.7 V to 3.6 V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

216 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

46 5V-tolerant (FT) pins detected

Package Envelope (D × E × A)D × E × A

14.00 × 14.00 × 1.60 mm (A1=0.10 mm)

Package family: LQFP (LQFP-100(14x14))

Pin Count & Lead PitchN / e

100 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, CAN, DAC, RTC/CLK, SWD/JTAG, UART

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol100 auto-grouped pins

IPC-7351B Land Pattern100 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-100(14x14))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

14.00 × 14.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.60mm · e=0.50mm

Pad Size (W × L)Level B

0.30 × 1.25 mm

Pins / Total PadsTopology

100P / 100Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit LQFP-100(14x14)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F722VET6 (LQFP-100(14x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F722VET6 (LQFP-100(14x14))?

Manufactured by ST, the STM32F722VET6 is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (PH0OSC IN -_: Multiplexed I/O & Peripheral Pin PH0OSC IN -_ (RTC/CLK)), 6 (PH1OSC OUT -_: Multiplexed I/O & Peripheral Pin PH1OSC OUT -_ (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32F722VET6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F722VET6 (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F722VET6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F722VET6 (ST, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32F722 / STM32F723 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	VBAT	Power_In	Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2	PC13	Digital_IO	Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
3	3V3	Power_In	3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4	NC	No_Connect	No Connect (Leave Floating)
5	PH0OSC IN -_	Digital_IO	Signal terminal PH0OSC IN -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0OSC IN -_. Supported peripheral buses: RTC/CLK.
6	PH1OSC OUT -_	Digital_IO	Signal terminal PH1OSC OUT -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1OSC OUT -_. Supported peripheral buses: RTC/CLK.
7	NRST	Digital_IO	Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8	PC0	Digital_IO	Signal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
9	PC1	Digital_IO	Signal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, I2C, ADC, RTC/CLK.
10	PC2	Digital_IO	Signal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, ADC.
11	PC3	Digital_IO	Signal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC.
12	VSSA	GND	0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
13	VREF+	Analog	Signal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
14	PA0WKUP -	Digital_IO	Signal terminal PA0WKUP - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0WKUP -. Supported peripheral buses: UART, ADC, PWM.
15	PA1	Digital_IO	Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
16	PA2	Digital_IO	Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: SPI, ADC, PWM.
17	PA3	Digital_IO	Signal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: ADC, PWM.
18	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
19	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
20	PA4	Digital_IO	Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
21	PA5	Digital_IO	Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC, PWM.
22	PA6	Digital_IO	Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: ADC.
23	PA7	Digital_IO	Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
24	PC4	Digital_IO	Signal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
25	PB0	Digital_IO	Signal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
26	PB1	Digital_IO	Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
27	PB2	Digital_IO	Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: SPI, I2C.
28	PB10	Digital_IO	Signal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
29	PB11	Digital_IO	Signal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: UART, PWM.
30	VCAP_1	Digital_IO	Signal terminal VCAP_1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_1. Supported peripheral buses: General.
31	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
33	PB12	Digital_IO	Signal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI.
34	PB13	Digital_IO	Signal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
35	PB14	Digital_IO	Signal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOUSART3RTS. Supported peripheral buses: SPI, PWM.
36	PB15	Digital_IO	Signal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, PWM, RTC/CLK.
37	PC6	Digital_IO	Signal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
38	PC7	Digital_IO	Signal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: PWM.
39	PC8	Digital_IO	Signal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: UART, PWM.
40	PC9	Digital_IO	Signal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: UART, I2C, RTC/CLK.
41	PA8	Digital_IO	Signal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: I2C, RTC/CLK.
42	PA9	Digital_IO	Signal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
43	PA10	Digital_IO	Signal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: PWM.
44	PA11	Digital_IO	Signal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: PWM, CAN.
45	PA12	Digital_IO	Signal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
46	PA13(JTMS - SWDIO)	Digital_IO	Signal terminal PA13(JTMS - SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13(JTMS - SWDIO). Supported peripheral buses: SWD/JTAG.
47	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
48	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
49	PA14(JTCK - SWCLK)	Digital_IO	Signal terminal PA14(JTCK - SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14(JTCK - SWCLK). Supported peripheral buses: SWD/JTAG.
50	PA15(JTDI)	Digital_IO	Signal terminal PA15(JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, SWD/JTAG.
51	PC10	Digital_IO	Signal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI.
52	PC11	Digital_IO	Signal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISOUSART3RX. Supported peripheral buses: UART, SPI.
53	PC12	Digital_IO	Signal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI.
54	PD2	Digital_IO	Signal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
55	PD8	Digital_IO	Signal terminal PD8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD8. Supported peripheral buses: General.
56	PD9	Digital_IO	Signal terminal PD9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD9. Supported peripheral buses: General.
57	PD10	Digital_IO	Signal terminal PD10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General.
58	PD11	Digital_IO	Signal terminal PD11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD11. Supported peripheral buses: UART, I2C.
59	PD12	Digital_IO	Signal terminal PD12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: UART, PWM.
60	PD13	Digital_IO	Signal terminal PD13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: SPI, PWM.
61	PD14	Digital_IO	Signal terminal PD14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: PWM.
62	PD15	Digital_IO	Signal terminal PD15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: PWM.
63	PC6	Digital_IO	Signal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
64	PC7	Digital_IO	Signal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.

4D Studio: STM32F722VET6 Permalink: /part/C132372 ST LQFP-100(14x14)All Packages All Manufacturers