Mechanical Dimensions & Land Pattern (LQFP-100(14x14))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.20 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-100(14x14) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32L552VET6Q (LQFP-100(14x14))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32L552VET6Q (LQFP-100(14x14))?
Manufactured by ST, the STM32L552VET6Q is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (PC14 - OSC3_2IN (PC14): Multiplexed I/O & Peripheral Pin PC14 - OSC3_2IN (PC14) (RTC/CLK)), 4 (NC: No Connect (Leave Floating)), 5 (PH0 - OSC_I N (PH0): Multiplexed I/O & Peripheral Pin PH0 - OSC_I N (PH0) (RTC/CLK)), 6 (PH1 - OSC_ OUT (PH1): Multiplexed I/O & Peripheral Pin PH1 - OSC_ OUT (PH1) (RTC/CLK)).
What are the IPC-7351B PCB Footprint dimensions for STM32L552VET6Q?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L552VET6Q (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L552VET6Q?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L552VET6Q (ST, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (100 pins) & STM32L552 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 2 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| 3 | PC14 - OSC3_2IN (PC14) | Digital_IO | Signal terminal PC14 - OSC3_2IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC3_2IN (PC14). Supported peripheral buses: RTC/CLK. |
| 4 | NC | No_Connect | No Connect (Leave Floating) |
| 5 | PH0 - OSC_I N (PH0) | Digital_IO | Signal terminal PH0 - OSC_I N (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC_I N (PH0). Supported peripheral buses: RTC/CLK. |
| 6 | PH1 - OSC_ OUT (PH1) | Digital_IO | Signal terminal PH1 - OSC_ OUT (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC_ OUT (PH1). Supported peripheral buses: RTC/CLK. |
| 7 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 8 | VSSA/ VREF - | GND | 0V electrical ground return terminal (VSSA/ VREF -) for internal core logic, I/O drivers, and analog sub-blocks. |
| 9 | VDDA/ VREF + | Power_In | Primary positive power supply input (VDDA/ VREF +) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 10 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 11 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_SCK. Supported peripheral buses: UART, SPI, I2C, ADC, PWM. |
| 12 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM. |
| 13 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM. |
| 14 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSSPI3NSS. Supported peripheral buses: UART, SPI, ADC, DAC. |
| 15 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC, PWM. |
| 16 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 17 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL, SPI1_MOSI. Supported peripheral buses: SPI, I2C, ADC, PWM. |
| 18 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 19 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM. |
| 20 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SMBA. Supported peripheral buses: I2C, RTC/CLK. |
| 21 | PB10 | Digital_IO | Signal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, I2C, PWM. |
| 22 | VDD12_1 | Power_In | Primary positive power supply input (VDD12_1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 23 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 24 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 25 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SMBA, SPI2_NSS. Supported peripheral buses: UART, SPI, I2C. |
| 26 | PB13 | Digital_IO | Signal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: UART, SPI, I2C, PWM. |
| 27 | PB14 | Digital_IO | Signal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA, SPI2_MISO. Supported peripheral buses: UART, SPI, I2C, PWM. |
| 28 | PB15 | Digital_IO | Signal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, I2C, PWM, RTC/CLK. |
| 29 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, SPI, RTC/CLK. |
| 30 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, PWM. |
| 31 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART, I2C, PWM. |
| 32 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: USB, UART, SPI, PWM. |
| 33 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: USB, UART, SPI. |
| 34 | PA13 (JTMS/ SWDI O) | Digital_IO | Signal terminal PA13 (JTMS/ SWDI O) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMS/ SWDI O). Supported peripheral buses: SWD/JTAG. |
| 35 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 36 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 37 | PA14 (JTCK/ SWCL K) | Digital_IO | Signal terminal PA14 (JTCK/ SWCL K) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, I2C4_SMBA. Supported peripheral buses: I2C, SWD/JTAG. |
| 38 | PA15 (JTDI) | Digital_IO | Signal terminal PA15 (JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSSSPI3NSS. Supported peripheral buses: UART, SPI, SWD/JTAG. |
| 39 | PC8 | Digital_IO | Signal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: PWM. |
| 40 | PE12 | Digital_IO | Signal terminal PE12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI, PWM. |
| 41 | PE13 | Digital_IO | Signal terminal PE13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE13. Supported peripheral buses: PWM. |
| 42 | PE14 | Digital_IO | Signal terminal PE14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE14. Supported peripheral buses: General. |
| 43 | PE15 | Digital_IO | Signal terminal PE15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE15. Supported peripheral buses: General. |
| 44 | PB10 | Digital_IO | Signal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General. |
| 45 | PB11 | Digital_IO | Signal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General. |
| 46 | VDDSMPS | Power_In | Primary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 47 | VLXSMPS | Digital_IO | Signal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General. |
| 48 | VSSSMPS | GND | 0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 49 | VSS | GND | Bottom exposed die attach pad (VSS) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |
| 50 | V15SMPS_1 | Digital_IO | Signal terminal V15SMPS_1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: V15SMPS_1. Supported peripheral buses: General. |
| 51 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 52 | PC11 | Digital_IO | Signal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI. |
| 53 | PC12 | Digital_IO | Signal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI. |
| 54 | PD2 | Digital_IO | Signal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART. |
| 55 | PD8 | Digital_IO | Signal terminal PD8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD8. Supported peripheral buses: General. |
| 56 | PD9 | Digital_IO | Signal terminal PD9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD9. Supported peripheral buses: General. |
| 57 | PD10 | Digital_IO | Signal terminal PD10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: UART, SPI. |
| 58 | PD11 | Digital_IO | Signal terminal PD11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SMBA. Supported peripheral buses: UART, SPI, I2C. |
| 59 | PD12 | Digital_IO | Signal terminal PD12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: UART, PWM. |
| 60 | PD13 | Digital_IO | Signal terminal PD13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: PWM. |
| 61 | PD14 | Digital_IO | Signal terminal PD14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: PWM. |
| 62 | PD15 | Digital_IO | Signal terminal PD15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: PWM. |
| 63 | PC6 | Digital_IO | Signal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General. |
| 64 | PC7 | Digital_IO | Signal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General. |