Mechanical Dimensions & Land Pattern (UFQFPN-48(7x7))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 0.55 mm
Pins / Total PadsTopology
48P / 49Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| C1, C2, C3 BOM | 3× 100nF (0.1µF) 50V X7R 0402 / 0603 | Digital supply decoupling caps for VDD_1..3 (Pins 24, 36, 48) — place < 1.5mm from each VDD pin. |
| C4 BOM | 4.7µF ~ 10µF 10V X5R 0603 / 0805 | Bulk decoupling capacitor for main VDD rail — place near 3.3V power entry to the MCU. |
| C5, C6 + FB1 BOM | 100nF + 1µF + Ferrite 600Ω@100MHz 0402 / 0603 | Analog rail filter for VDDA/VSSA (Pins 8, 9) 12-bit ADC — isolate digital switching noise. |
| Y1 + C7, C8 BOM | 8MHz Crystal (CL=12pF) + 2× 18pF NP0 SMD-3225 + 0402 | Main HSE oscillator crystal (Pin 5 PD0, Pin 6 PD1) — route matched traces < 4mm with GND guard ring. |
| STM32F103CBT6 STMicroelectronics | 100% Drop-in | 100% Drop-in (128KB Flash Upgrade) — identical LQFP-48 pinout with doubled Flash capacity. |
| GD32F103C8T6 GigaDevice | Pin-to-Pin LQFP-48 (108MHz) | Pin-to-Pin LQFP-48 (108MHz) — higher core clock; verify Flash wait-states & USB timing. |
| APM32F103C8T6 Geehy | Pin-to-Pin LQFP-48 (96MHz) | Pin-to-Pin LQFP-48 (96MHz) — direct hardware replacement, register-compatible with STM32F1. |
Technical Frequently Asked Questions (FAQ) — STM32F103CBU6TR (UFQFPN-48(7x7))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32F103CBU6TR (UFQFPN-48(7x7))?
Manufactured by ST, the STM32F103CBU6TR is housed in a UFQFPN-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (PC14-OSC32_IN: Multiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)), 4 (PC15-OSC32_OUT: Multiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)), 5 (PD0-OSC_IN: Multiplexed I/O & Peripheral Pin PD0-OSC_IN (RTC/CLK)), 6 (PD1-OSC_OUT: Multiplexed I/O & Peripheral Pin PD1-OSC_OUT (RTC/CLK)).
What are the IPC-7351B PCB Footprint dimensions for STM32F103CBU6TR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F103CBU6TR (UFQFPN-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.60 × 5.60 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F103CBU6TR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F103CBU6TR (ST, UFQFPN-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (48 pins) & STM32F103 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 2 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: TAMPER-RTC, RTC_OUT, RTC_CALIB. Supported peripheral buses: RTC/CLK. |
| 3 | PC14-OSC32_IN | Digital_IO | Signal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC32_IN, PC14. Supported peripheral buses: RTC/CLK. |
| 4 | PC15-OSC32_OUT | Digital_IO | Signal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC32_OUT, PC15. Supported peripheral buses: RTC/CLK. |
| 5 | PD0-OSC_IN | Digital_IO | Signal terminal PD0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN, PD0. Supported peripheral buses: RTC/CLK. |
| 6 | PD1-OSC_OUT | Digital_IO | Signal terminal PD1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT, PD1. Supported peripheral buses: RTC/CLK. |
| 7 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 8 | VSSA | GND | 0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| 9 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 10 | PA0-WKUP | Analog | Signal terminal PA0-WKUP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: WKUP, USART2_CTS, ADC12_IN0, TIM2_CH1_ETR. Supported peripheral buses: UART, ADC, PWM. |
| 11 | PA1 | Analog | Signal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USART2_RTS, ADC12_IN1, TIM2_CH2. Supported peripheral buses: UART, ADC, PWM. |
| 12 | PA2 | Analog | Signal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USART2_TX, ADC12_IN2, TIM2_CH3. Supported peripheral buses: UART, ADC, PWM. |
| 13 | PA3 | Analog | Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USART2_RX, ADC12_IN3, TIM2_CH4. Supported peripheral buses: UART, ADC, PWM. |
| 14 | PA4 | Analog | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, USART2_CK, ADC12_IN4. Supported peripheral buses: UART, SPI, ADC. |
| 15 | PA5 | Analog | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK, ADC12_IN5. Supported peripheral buses: SPI, ADC. |
| 16 | PA6 | Analog | Signal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO, ADC12_IN6, TIM3_CH1, TIM1_BKIN. Supported peripheral buses: SPI, ADC, PWM. |
| 17 | PA7 | Analog | Signal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI, ADC12_IN7, TIM3_CH2, TIM1_CH1N. Supported peripheral buses: SPI, ADC, PWM. |
| 18 | PB0 | Analog | Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: ADC12_IN8, TIM3_CH3, TIM1_CH2N. Supported peripheral buses: ADC, PWM. |
| 19 | PB1 | Analog | Signal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: ADC12_IN9, TIM3_CH4, TIM1_CH3N. Supported peripheral buses: ADC, PWM. |
| 20 | PB2/BOOT1 | Digital_IO | Signal terminal PB2/BOOT1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: BOOT1, PB2. Supported peripheral buses: General. |
| 21 | PB10 | Digital_IO | Signal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL, USART3_TX, TIM2_CH3. Supported peripheral buses: UART, I2C, PWM. |
| 22 | PB11 | Digital_IO | Signal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA, USART3_RX, TIM2_CH4. Supported peripheral buses: UART, I2C, PWM. |
| 23 | VSS_1 | GND | 0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks. |
| 24 | VDD_1 | Power_In | Primary positive power supply input (VDD_1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 25 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, I2C2_SMBA, USART3_CK, TIM1_BKIN. Supported peripheral buses: UART, SPI, I2C. |
| 26 | PB13 | Digital_IO | Signal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK, USART3_CTS, TIM1_CH1N. Supported peripheral buses: UART, SPI, PWM. |
| 27 | PB14 | Digital_IO | Signal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO, USART3_RTS, TIM1_CH2N. Supported peripheral buses: UART, SPI, PWM. |
| 28 | PB15 | Digital_IO | Signal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI, TIM1_CH3N. Supported peripheral buses: SPI, PWM. |
| 29 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USART1_CK, TIM1_CH1, MCO. Supported peripheral buses: UART, PWM, RTC/CLK. |
| 30 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USART1_TX, TIM1_CH2. Supported peripheral buses: UART, PWM. |
| 31 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USART1_RX, TIM1_CH3. Supported peripheral buses: UART, PWM. |
| 32 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USB_DM, CAN_RX, USART1_CTS, TIM1_CH4. Supported peripheral buses: USB, UART, PWM, CAN. |
| 33 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USB_DP, CAN_TX, USART1_RTS, TIM1_ETR. Supported peripheral buses: USB, UART, CAN. |
| 34 | PA13 | Digital_IO | Signal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTMS, SWDIO. Supported peripheral buses: SWD/JTAG. |
| 35 | VSS_2 | GND | 0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks. |
| 36 | VDD_2 | Power_In | Primary positive power supply input (VDD_2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 37 | PA14 | Digital_IO | Signal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTCK, SWCLK. Supported peripheral buses: SWD/JTAG. |
| 38 | PA15 | Digital_IO | Signal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTDI, SPI1_NSS, TIM2_CH1_ETR. Supported peripheral buses: SPI, PWM, SWD/JTAG. |
| 39 | PB3 | Digital_IO | Signal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTDO, SPI1_SCK, TIM2_CH2, TRACESWO. Supported peripheral buses: SPI, PWM, SWD/JTAG. |
| 40 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: NJTRST, SPI1_MISO, TIM3_CH1. Supported peripheral buses: SPI, PWM, SWD/JTAG. |
| 41 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSI, TIM3_CH2. Supported peripheral buses: SPI, I2C, PWM. |
| 42 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL, TIM4_CH1, USART1_TX. Supported peripheral buses: UART, I2C, PWM. |
| 43 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA, TIM4_CH2, USART1_RX. Supported peripheral buses: UART, I2C, PWM. |
| 44 | BOOT0 | Digital_IO | Signal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General. |
| 45 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: TIM4_CH3, I2C1_SCL, CAN_RX. Supported peripheral buses: I2C, PWM, CAN. |
| 46 | PB9 | Digital_IO | Signal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: TIM4_CH4, I2C1_SDA, CAN_TX. Supported peripheral buses: I2C, PWM, CAN. |
| 47 | VSS_3 | GND | 0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks. |
| 48 | VDD_3 | Power_In | Primary positive power supply input (VDD_3) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |