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NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL) — Symbol, Footprint IPC-7351B & 3D STEP Model

NUCLEO-L031K6

STID: C94083DIP-30_L51.0-W17.8-P2.54-LS15.2-TL · 30 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL)1TXD2RXD3RST4GND5D26D37D48D59D610D711D812D913D1014D1115D1230VIN29GND28RST275V26A725A624A523A422A321A220A119A018REF173V316D13Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.825.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930E=13.70mm · Pitch e=2.54mmD=37.56mm-18-16-14-12-10-8-6-4-20246810121416182927252321191715131197531-1-3-5-7-9-11-13-15-17-19-21-23-25-27-29mm
3. 3D CAD MODEL
Package Body: 13.70mm × 37.56mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (30/30)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
2RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
3RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
4GNDGNDGround Reference Pin (GND)
5D2I/OMultiplexed I/O & Peripheral Pin D2 (General)
6D3I/OMultiplexed I/O & Peripheral Pin D3 (General)
7D4I/OMultiplexed I/O & Peripheral Pin D4 (General)
8D5I/OMultiplexed I/O & Peripheral Pin D5 (General)
9D6I/OMultiplexed I/O & Peripheral Pin D6 (General)
10D7I/OMultiplexed I/O & Peripheral Pin D7 (General)
11D8I/OMultiplexed I/O & Peripheral Pin D8 (General)
12D9I/OMultiplexed I/O & Peripheral Pin D9 (General)
13D10I/OMultiplexed I/O & Peripheral Pin D10 (General)
14D11I/OMultiplexed I/O & Peripheral Pin D11 (General)
15D12I/OMultiplexed I/O & Peripheral Pin D12 (General)
16D13I/OMultiplexed I/O & Peripheral Pin D13 (General)
173V3PowerPower Supply Input (3V3 — 3.3V / 5.0V Standard Logic)
18REFI/OMultiplexed I/O & Peripheral Pin REF (General)
19A0I/OMultiplexed I/O & Peripheral Pin A0 (General)
20A1I/OMultiplexed I/O & Peripheral Pin A1 (General)
21A2I/OMultiplexed I/O & Peripheral Pin A2 (General)
22A3I/OMultiplexed I/O & Peripheral Pin A3 (General)
23A4I/OMultiplexed I/O & Peripheral Pin A4 (General)
24A5I/OMultiplexed I/O & Peripheral Pin A5 (General)
25A6I/OMultiplexed I/O & Peripheral Pin A6 (General)
26A7I/OMultiplexed I/O & Peripheral Pin A7 (General)
275VPowerPower Supply Input (5V — 3.3V / 5.0V Standard Logic)
28RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
29GNDGNDGround Reference Pin (GND)
30VINPowerPower Supply Input (VIN — 3.3V / 5.0V Standard Logic)
PIN 1 TXD
I/O
Multiplexed I/O & Peripheral Pin TXD (UART)
Design note: Signal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: NUCLEO-L031K6 (ST · DIP-30_L51.0-W17.8-P2.54-LS15.2-TL)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL) - 2. Standard Pinout (Top View)
True package pinout (30 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL) - 4. Package Dimensions (D×E×A)
DIP-30_L51.0-W17.8-P2.54-LS15.2-TL · 13.70×37.56mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL) - 5. Recommended Land Pattern
IPC-7351B Footprint (30 Pads)Expand ›
6. Application SchematicSCHEMATIC
NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for NUCLEO
P1 · p01_fig02784×648px
NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL) — 1. Picture not contractual
1. Picture not contractual
P1 · p01_fig03878×293px
NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL) — June 2016 DocID028107 Rev 3 1/4
June 2016 DocID028107 Rev 3 1/4
P1 · p01_fig02P1
NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P1 · p01_fig01All Packages in PDF
NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL) —  Reset push-button
 Reset push-button

Technical Specifications & Part Details (NUCLEO-L031K6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL) is a 30-pin standard electronic & interconnect component featuring a 37.56 × 13.70 × 4.20 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, JTAG / SWD, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
37.56 × 13.70 × 4.20 mm (A1=0.51 mm)
Package family: DIP (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL)
Pin Count & Lead PitchN / e
30 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, JTAG / SWD, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol30 auto-grouped pins
OK
IPC-7351B Land Pattern30 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
37.56 × 13.70 mm
Height (A) & Pitch (e)IPC-7351B
A=4.20mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
30P / 30Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
DIP-30_L51.0-W17.8-P2.54-LS15.2-TL
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL)?

Manufactured by ST, the NUCLEO-L031K6 is housed in a DIP-30_L51.0-W17.8-P2.54-LS15.2-TL package with 30 pins and a 2.54 mm lead pitch. Key pins include: 1 (TXD: Multiplexed I/O & Peripheral Pin TXD (UART)), 2 (RXD: Multiplexed I/O & Peripheral Pin RXD (UART)), 3 (RST: Multiplexed I/O & Peripheral Pin RST (General)), 4 (GND: Ground Reference Pin (GND)), 5 (D2: Multiplexed I/O & Peripheral Pin D2 (General)), 6 (D3: Multiplexed I/O & Peripheral Pin D3 (General)).

What are the IPC-7351B PCB Footprint dimensions for NUCLEO-L031K6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), NUCLEO-L031K6 (DIP-30_L51.0-W17.8-P2.54-LS15.2-TL) has a nominal body envelope of 13.70 × 37.56 mm, pitch e = 2.54 mm, and 30 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for NUCLEO-L031K6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for NUCLEO-L031K6 (ST, DIP-30_L51.0-W17.8-P2.54-LS15.2-TL) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (30 pins) & NUCLEO Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1TXDDigital_IOSignal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
2RXDDigital_IOSignal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
3RSTDigital_IOSignal terminal RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
4GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
5D2Digital_IOSignal terminal D2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D2. Supported peripheral buses: General.
6D3Digital_IOSignal terminal D3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D3. Supported peripheral buses: General.
7D4Digital_IOSignal terminal D4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D4. Supported peripheral buses: General.
8D5Digital_IOSignal terminal D5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D5. Supported peripheral buses: General.
9D6Digital_IOSignal terminal D6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D6. Supported peripheral buses: General.
10D7Digital_IOSignal terminal D7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D7. Supported peripheral buses: General.
11D8Digital_IOSignal terminal D8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D8. Supported peripheral buses: General.
12D9Digital_IOSignal terminal D9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D9. Supported peripheral buses: General.
13D10Digital_IOSignal terminal D10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D10. Supported peripheral buses: General.
14D11Digital_IOSignal terminal D11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D11. Supported peripheral buses: General.
15D12Digital_IOSignal terminal D12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D12. Supported peripheral buses: General.
16D13Digital_IOSignal terminal D13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D13. Supported peripheral buses: General.
173V3Power_InPrimary positive power supply input (3V3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
18REFDigital_IOSignal terminal REF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: REF. Supported peripheral buses: General.
19A0Digital_IOSignal terminal A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
20A1Digital_IOSignal terminal A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
21A2Digital_IOSignal terminal A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
22A3Digital_IOSignal terminal A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3. Supported peripheral buses: General.
23A4Digital_IOSignal terminal A4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A4. Supported peripheral buses: General.
24A5Digital_IOSignal terminal A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A5. Supported peripheral buses: General.
25A6Digital_IOSignal terminal A6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A6. Supported peripheral buses: General.
26A7Digital_IOSignal terminal A7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A7. Supported peripheral buses: General.
275VPower_InPrimary positive power supply input (5V) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
28RSTDigital_IOSignal terminal RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
29GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
30VINPower_InPrimary positive power supply input (VIN) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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