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STM32L562QEI6Q (UFBGA-132(7x7x0.5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L562QEI6Q

STID: C911176UFBGA-132(7x7x0.5) · 132 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L562QEI6Q (UFBGA-132(7x7x0.5))A1VDDA2PC10A3PE1A4PB9A5PB6A6PB5A7PD6A8PD5A9VDDA10PC11A11PA15A12VDDUSBB1VDDU SBB2VSSB3PC12B4V15S_MPS 2B5VSSB6PB4 (NJTR STB7PC13B8PD4B9VBATB10PC12B11PC10B12PA12C1PA11C2PA12C3PC11C4PE0C5PB8C6PB6C7PB8C8IOC8C9PC14 - OSC3_C10PA13C11PA14C12PA11D1PA9D2PA13 (JTMS/ D3PA14 (JTCK/ D4PG9D5PB7D6PB7D7PH3 - BOOT 0D8VDDIO 2D9PH0 - OSC_I D10PA9D11PA10D12PA8E1PC6E2PC7E3PA10E4VSSE9NRSTE10PC7E11PC9E12PC8F1PB15F2PB13F3PC8F4PA8F6VSSF7VDDF9PG6F10PG7F11PC6F12PG8M12PD10M11V15SMPS_1M10VLXSMPSM9VDDSMPSM8PE13M7PE9M6PG0M5PF13M4PB0M3PC4M2OPAM_P2VI NMM1PA5L12PD8L11PB12L10VSSSMPSL9PB11L8PE15L7PE11L6PF15L5PF12L4PB1L3PA4L2PA6L1PA3K12PB15K11PB14K10PB13K9PB10K8PE14K7PE7K6PG1K5PF11K4PB2K3PA7K2PA2K1VDDAJ12PD12J11PD11J10PD9J9VDDJ8PE12J7PA7J6PE8J5PF14J4PE13J3PB10J2PB11J1VDD12_1H12PD15H11PD13H10PD14H9VSSH4PE14H3PE15H2PC0H1VDDG12PG5G11PG3G10PG2G9PG4G7VSSG6VDDG4PC4G3PC9G2PB12G1PB14Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.888.983.878.773.768.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6-73.7-78.7-83.8-88.9mm
2. 2D FOOTPRINT
A1A2A3A4A5A6A7A8A9A10A11A12B1B2B3B4B5B6B7B8B9B10B11B12C1C2C3C4C5C6C7C8C9C10C11C12D1D2D3D4D5D6D7D8D9D10D11D12E1E2E3E4E9E10E11E12F1F2F3F4F6F7F9F10F11F12G1G2G3G4G6G7G9G10G11G12H1H2H3H4H9H10H11H12J1J2J3J4J5J6J7J8J9J10J11J12K1K2K3K4K5K6K7K8K9K10K11K12L1L2L3L4L5L6L7L8L9L10L11L12M1M2M3M4M5M6M7M8M9M10M11M12E=7.00mm · Pitch e=0.50mmD=7.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (132/132)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
A2PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
A3PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
A4PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI)
A5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
A6PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C, PWM)
A7PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
A8PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
A9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
A10PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
A11PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
A12VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
B1VDDU SBPowerPower Supply Input (VDDU SB — 3.3V VDD (Max 4.0V))
B2VSSGNDGround Reference Pin (VSS)
B3PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI)
B4V15S_MPS 2I/OMultiplexed I/O & Peripheral Pin V15S_MPS 2 (General)
B5VSSGNDGround Reference Pin (VSS)
B6PB4 (NJTR ST)I/OMultiplexed I/O & Peripheral Pin PB4 (NJTR ST) (UART, SPI, I2C, SWD/JTAG)
B7PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
B8PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
B9VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B10PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
B11PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
B12PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
C1PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, SPI, PWM)
C2PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, SPI)
C3PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI)
C4PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
C5PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
C6PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C, PWM)
C7PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C, PWM)
C8IOC8I/OGeneral Purpose Digital I/O Pin IOC8
C9PC14 - OSC3_2IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC3_2IN (PC14) (RTC/CLK)
C10PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
C11PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
C12PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
D1PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, PWM)
D2PA13 (JTMS/ SWDI O)I/OMultiplexed I/O & Peripheral Pin PA13 (JTMS/ SWDI O) (SWD/JTAG)
D3PA14 (JTCK/ SWCL K)I/OMultiplexed I/O & Peripheral Pin PA14 (JTCK/ SWCL K) (I2C, SWD/JTAG)
D4PG9I/OMultiplexed I/O & Peripheral Pin PG9 (UART, SPI)
D5PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
D6PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C, PWM)
D7PH3 - BOOT 0I/OMultiplexed I/O & Peripheral Pin PH3 - BOOT 0 (General)
D8VDDIO 2PowerPower Supply Input (VDDIO 2 — 3.3V VDD (Max 4.0V))
D9PH0 - OSC_I N (PH0)I/OMultiplexed I/O & Peripheral Pin PH0 - OSC_I N (PH0) (RTC/CLK)
D10PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
D11PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
D12PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
E1PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
E2PC7I/OMultiplexed I/O & Peripheral Pin PC7 (PWM)
E3PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, I2C, PWM)
E4VSSGNDGround Reference Pin (VSS)
E9NRSTISystem Enable & Hardware Reset (NRST)
E10PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
E11PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E12PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
F1PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, I2C, PWM, RTC/CLK)
F2PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, I2C, PWM)
F3PC8I/OMultiplexed I/O & Peripheral Pin PC8 (PWM)
F4PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, SPI, RTC/CLK)
F6VSSGNDGround Reference Pin (VSS)
F7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F9PG6I/OMultiplexed I/O & Peripheral Pin PG6 (UART, I2C)
F10PG7I/OMultiplexed I/O & Peripheral Pin PG7 (General)
F11PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
F12PG8I/OMultiplexed I/O & Peripheral Pin PG8 (I2C)
G1PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, I2C, PWM)
G2PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
G3PC9I/OMultiplexed I/O & Peripheral Pin PC9 (USB, PWM)
G4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
G6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G7VSSGNDGround Reference Pin (VSS)
G9PG4I/OMultiplexed I/O & Peripheral Pin PG4 (SPI)
G10PG2I/OMultiplexed I/O & Peripheral Pin PG2 (SPI)
G11PG3I/OMultiplexed I/O & Peripheral Pin PG3 (SPI)
G12PG5I/OMultiplexed I/O & Peripheral Pin PG5 (UART, SPI)
H1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
H2PC0I/OMultiplexed I/O & Peripheral Pin PC0 (I2C, ADC)
H3PE15I/OMultiplexed I/O & Peripheral Pin PE15 (SPI)
H4PE14I/OMultiplexed I/O & Peripheral Pin PE14 (SPI, PWM)
H9VSSGNDGround Reference Pin (VSS)
H10PD14I/OMultiplexed I/O & Peripheral Pin PD14 (PWM)
H11PD13I/OMultiplexed I/O & Peripheral Pin PD13 (PWM)
H12PD15I/OMultiplexed I/O & Peripheral Pin PD15 (PWM)
J1VDD12_1PowerPower Supply Input (VDD12_1 — 3.3V VDD (Max 4.0V))
J2PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C, PWM)
J3PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, SPI, I2C, PWM)
J4PE13I/OMultiplexed I/O & Peripheral Pin PE13 (PWM)
J5PF14I/OMultiplexed I/O & Peripheral Pin PF14 (I2C)
J6PE8I/OMultiplexed I/O & Peripheral Pin PE8 (SPI, PWM)
J7PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, I2C, ADC, PWM)
J8PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
J9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
J10PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
J11PD11I/OMultiplexed I/O & Peripheral Pin PD11 (UART, SPI, I2C)
J12PD12I/OMultiplexed I/O & Peripheral Pin PD12 (UART, PWM)
K1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
K2PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
K3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
K4PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C, RTC/CLK)
K5PF11I/OMultiplexed I/O & Peripheral Pin PF11 (General)
K6PG1I/OMultiplexed I/O & Peripheral Pin PG1 (General)
K7PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
K8PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
K9PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
K10PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
K11PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
K12PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
L1PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
L2PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC, PWM)
L3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
L4PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
L5PF12I/OMultiplexed I/O & Peripheral Pin PF12 (General)
L6PF15I/OMultiplexed I/O & Peripheral Pin PF15 (I2C)
L7PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
L8PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
L9PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
L10VSSSMPSGNDGround Reference Pin (VSSSMPS)
L11PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
L12PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
M1PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
M2OPAM_P2VI NMI/OMultiplexed I/O & Peripheral Pin OPAM_P2VI NM (General)
M3PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
M4PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
M5PF13I/OMultiplexed I/O & Peripheral Pin PF13 (I2C)
M6PG0I/OMultiplexed I/O & Peripheral Pin PG0 (General)
M7PE9I/OMultiplexed I/O & Peripheral Pin PE9 (PWM)
M8PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
M9VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
M10VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
M11V15SMPS_1I/OMultiplexed I/O & Peripheral Pin V15SMPS_1 (General)
M12PD10I/OMultiplexed I/O & Peripheral Pin PD10 (UART, SPI)
PIN A1 VDD
Power
Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L562QEI6Q (ST · UFBGA-132(7x7x0.5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) - 2. Standard Pinout (Top View)
True package pinout (132 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) - 4. Package Dimensions (D×E×A)
UFBGA-132(7x7x0.5) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (132 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for STM32L562
P87 · p87_fig01EXACT PACKAGE
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) — Figure 21. STM32L562xx UFBGA132 ballout
Figure 21. STM32L562xx UFBGA132 ballout
P87 · p87_fig02EXACT PACKAGE
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) — K
K
P325 · p325_fig01EXACT PACKAGE
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) — Figure 91. UFBGA132 outline
Figure 91. UFBGA132 outline
P326 · p326_fig01EXACT PACKAGE
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) — Figure 92. UFBGA132 recommended footprint
Figure 92. UFBGA132 recommended footprint
P1 · p01_fig011751×860px
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) — • 62 μA/MHz Run mode @ 3 V (SMPS step-down converter mode)
• 62 μA/MHz Run mode @ 3 V (SMPS step-down converter mode)
P81 · p81_fig011751×2191px
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) — Figure 10. STM32L562xx LQFP48 pinout
Figure 10. STM32L562xx LQFP48 pinout
P81 · p81_fig01P81
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) — Datasheet Page 81 (p81_fig01)
Datasheet Page 81 (p81_fig01)
P141 · p141_fig011560×1866px
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) — Figure 27. STM32L552xx and STM32L562xx power supply overview
Figure 27. STM32L552xx and STM32L562xx power supply overview
P141 · p141_fig01P141
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) — Datasheet Page 141 (p141_fig01)
Datasheet Page 141 (p141_fig01)
P218 · p218_fig011546×702px
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) — Figure 35. Typical application with an 8 MHz crystal
Figure 35. Typical application with an 8 MHz crystal
P219 · p219_fig011546×702px
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) — Figure 36. Typical application with a 32.768 kHz crystal
Figure 36. Typical application with a 32.768 kHz crystal
P311 · p311_fig011546×1076px
STM32L562QEI6Q (UFBGA-132(7x7x0.5)) — Figure 77. LQFP48 recommended footprint
Figure 77. LQFP48 recommended footprint
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (STM32L562QEI6Q)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L562QEI6Q (UFBGA-132(7x7x0.5)) is a 132-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
110 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
67 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.60 mm (A1=0.20 mm)
Package family: BGA (UFBGA-132(7x7x0.5))
Pin Count & Lead PitchN / e
132 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol132 auto-grouped pins
OK
IPC-7351B Land Pattern132 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-132(7x7x0.5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 0.30 mm
Pins / Total PadsTopology
132P / 132Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-132(7x7x0.5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L562QEI6Q (UFBGA-132(7x7x0.5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L562QEI6Q (UFBGA-132(7x7x0.5))?

Manufactured by ST, the STM32L562QEI6Q is housed in a UFBGA-132(7x7x0.5) package with 132 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), A2 (PC10: Multiplexed I/O & Peripheral Pin PC10 (UART, SPI)), A3 (PE1: Multiplexed I/O & Peripheral Pin PE1 (General)), A4 (PB9: Multiplexed I/O & Peripheral Pin PB9 (SPI)), A5 (PB6: Multiplexed I/O & Peripheral Pin PB6 (General)), A6 (PB5: Multiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C, PWM)).

What are the IPC-7351B PCB Footprint dimensions for STM32L562QEI6Q?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L562QEI6Q (UFBGA-132(7x7x0.5)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 132 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L562QEI6Q?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L562QEI6Q (ST, UFBGA-132(7x7x0.5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (132 pins) & STM32L562 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A2PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI.
A3PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
A4PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI.
A5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
A6PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSI, SPI3_MOSI. Supported peripheral buses: UART, SPI, I2C, PWM.
A7PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
A8PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
A9VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A10PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
A11PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
A12VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B1VDDU SBPower_InPrimary positive power supply input (VDDU SB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B3PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI.
B4V15S_MPS 2Digital_IOSignal terminal V15S_MPS 2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: V15S_MPS 2. Supported peripheral buses: General.
B5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B6PB4 (NJTR ST)Digital_IOSignal terminal PB4 (NJTR ST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA, SPI1_MISO, SPI3_MISO. Supported peripheral buses: UART, SPI, I2C, SWD/JTAG.
B7PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
B8PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
B9VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B10PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
B11PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
B12PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
C1PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: USB, UART, SPI, PWM.
C2PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: USB, UART, SPI.
C3PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI.
C4PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
C5PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
C6PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART, I2C, PWM.
C7PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C, PWM.
C8IOC8Digital_IOGeneral Purpose Digital I/O Pin IOC8
C9PC14 - OSC3_2IN (PC14)Digital_IOSignal terminal PC14 - OSC3_2IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC3_2IN (PC14). Supported peripheral buses: RTC/CLK.
C10PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
C11PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
C12PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
D1PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, PWM.
D2PA13 (JTMS/ SWDI O)Digital_IOSignal terminal PA13 (JTMS/ SWDI O) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMS/ SWDI O). Supported peripheral buses: SWD/JTAG.
D3PA14 (JTCK/ SWCL K)Digital_IOSignal terminal PA14 (JTCK/ SWCL K) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, I2C4_SMBA. Supported peripheral buses: I2C, SWD/JTAG.
D4PG9Digital_IOSignal terminal PG9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI.
D5PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
D6PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART, I2C, PWM.
D7PH3 - BOOT 0Digital_IOSignal terminal PH3 - BOOT 0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH3 - BOOT 0. Supported peripheral buses: General.
D8VDDIO 2Power_InPrimary positive power supply input (VDDIO 2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D9PH0 - OSC_I N (PH0)Digital_IOSignal terminal PH0 - OSC_I N (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC_I N (PH0). Supported peripheral buses: RTC/CLK.
D10PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
D11PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
D12PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
E1PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
E2PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: PWM.
E3PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART, I2C, PWM.
E4VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E9NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E10PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
E11PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E12PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
F1PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, I2C, PWM, RTC/CLK.
F2PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: UART, SPI, I2C, PWM.
F3PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: PWM.
F4PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, SPI, RTC/CLK.
F6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F9PG6Digital_IOSignal terminal PG6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SMBA. Supported peripheral buses: UART, I2C.
F10PG7Digital_IOSignal terminal PG7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG7. Supported peripheral buses: General.
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