UFQFPN-48-EP(7x7) · 49P
IPC-7351B
49P7.0×7.0×0.60mmP=0.5mm
STM32L4P5CEU / STM32L4P5VGY / STM32L4P5QGI (UFQFPN-48-EP(7x7))
Synchronized Pinout (Symbol / 2D / 3D) (49/49)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | VBAT | Power | Power Supply Input (VBAT — 3.3V VDD (Max 4.0V)) |
| 2 | PC13 | I/O | Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK) |
| 3 | PC14 - OSC32_I N(PC14) | I/O | Multiplexed I/O & Peripheral Pin PC14 - OSC32_I N(PC14) (RTC/CLK) |
| 4 | NC | NC | No Connect (Leave Floating) |
| 5 | PH0-OSC_IN | I/O | Multiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK) |
| 6 | PH1-OSC_OUT | I/O | Multiplexed I/O & Peripheral Pin PH1-OSC_OUT (RTC/CLK) |
| 7 | NRST | I | System Enable & Hardware Reset (NRST) |
| 8 | VSSA/VREF- | GND | Ground Reference Pin (VSSA/VREF-) |
| 9 | VDDA/VREF+ | Power | Power Supply Input (VDDA/VREF+ — 3.3V VDD (Max 4.0V)) |
| 10 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (General) |
| 11 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (General) |
| 12 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (General) |
| 13 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (General) |
| 14 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (General) |
| 15 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (General) |
| 16 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (General) |
| 17 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (General) |
| 18 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (General) |
| 19 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (General) |
| 20 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (General) |
| 21 | PB10 | I/O | Multiplexed I/O & Peripheral Pin PB10 (General) |
| 22 | PB11 | I/O | Multiplexed I/O & Peripheral Pin PB11 (General) |
| 23 | VSS | GND | Ground Reference Pin (VSS) |
| 24 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 25 | PB12 | I/O | Multiplexed I/O & Peripheral Pin PB12 (General) |
| 26 | PB13 | I/O | Multiplexed I/O & Peripheral Pin PB13 (General) |
| 27 | PB14 | I/O | Multiplexed I/O & Peripheral Pin PB14 (General) |
| 28 | PB15 | I/O | Multiplexed I/O & Peripheral Pin PB15 (General) |
| 29 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (General) |
| 30 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (General) |
| 31 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (General) |
| 32 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (General) |
| 33 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (General) |
| 34 | PA13 | I/O | Multiplexed I/O & Peripheral Pin PA13 (General) |
| 35 | VSS | GND | Ground Reference Pin (VSS) |
| 36 | VDDUSB | Power | Power Supply Input (VDDUSB — 3.3V VDD (Max 4.0V)) |
| 37 | PA14 | I/O | Multiplexed I/O & Peripheral Pin PA14 (General) |
| 38 | PA15 | I/O | Multiplexed I/O & Peripheral Pin PA15 (General) |
| 39 | PB3 | I/O | Multiplexed I/O & Peripheral Pin PB3 (General) |
| 40 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (General) |
| 41 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (General) |
| 42 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (General) |
| 43 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (General) |
| 44 | PH3-BOOT0 | I/O | Multiplexed I/O & Peripheral Pin PH3-BOOT0 (General) |
| 45 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (General) |
| 46 | PB9 | I/O | Multiplexed I/O & Peripheral Pin PB9 (General) |
| 47 | VSS | GND | Ground Reference Pin (VSS) |
| 48 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 49 | EP | GND | Exposed Thermal & Ground Pad (EP) |
PIN 1 VBAT
PowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 35 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
UFQFPN-48-EP(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (35 figures · Page 1/3)
Showing 1–12 of 35 uncropped original figures for STM32L4P5CEU / STM32L4P5VGY / STM32L4P5QGI
P66 · p66_fig01EXACT PACKAGE
P66 · p66_fig02EXACT PACKAGE
P281 · p281_fig01EXACT PACKAGE
P282 · p282_fig01EXACT PACKAGE
P1 · p01_fig011751×640px
P65 · p65_fig011557×1031px
P65 · p65_fig021546×1341px
P66 · p66_fig01P66
P135 · p135_fig011751×2091px
P135 · p135_fig01P135
P187 · p187_fig011546×702px
P188 · p188_fig011546×702px
Page 1 / 3 (35 extracted figures)
Technical Specifications & Part Details (STM32L4P5CEU6)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32L4P5CEU6 (UFQFPN-48-EP(7x7)) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
120 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
3 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.60 mm (A1=0.03 mm)
Package family: QFN (UFQFPN-48-EP(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3-BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol49 auto-grouped pins
IPC-7351B Land Pattern49 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteEPAD 5.50×5.50mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32L4P5CEU / STM32L4P5VGY / STM32L4P5QGI (5)
LQFP-64(10x10) · 64P
IPC-7351B
64P10.0×10.0×1.60mmP=0.5mm
STM32L4P5CEU / STM32L4P5VGY / STM32L4P5QGI (LQFP-64(10x10))
WLCSP-100(4.1x4.6) · 100P
100P4.6×4.1×0.55mmP=0.4mm
STM32L4P5CEU / STM32L4P5VGY / STM32L4P5QGI (WLCSP-100(4.1x4.6))
UFBGA-132 · 132P
IPC-7351B
132P7.0×7.0×0.60mmP=0.5mm
STM32L4P5CEU / STM32L4P5VGY / STM32L4P5QGI (UFBGA-132)
LQFP-144(20x20) · 144P
IPC-7351B
144P20.0×20.0×1.60mmP=0.5mm
STM32L4P5CEU / STM32L4P5VGY / STM32L4P5QGI (LQFP-144(20x20))
Mechanical Dimensions & Land Pattern (UFQFPN-48-EP(7x7))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 0.55 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit UFQFPN-48-EP(7x7) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32L4P5CEU6 (UFQFPN-48-EP(7x7))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32L4P5CEU6 (UFQFPN-48-EP(7x7))?
Manufactured by ST, the STM32L4P5CEU6 is housed in a UFQFPN-48-EP(7x7) package with 49 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (PC14 - OSC32_I N(PC14): Multiplexed I/O & Peripheral Pin PC14 - OSC32_I N(PC14) (RTC/CLK)), 4 (NC: No Connect (Leave Floating)), 5 (PH0-OSC_IN: Multiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK)), 6 (PH1-OSC_OUT: Multiplexed I/O & Peripheral Pin PH1-OSC_OUT (RTC/CLK)).
What are the IPC-7351B PCB Footprint dimensions for STM32L4P5CEU6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L4P5CEU6 (UFQFPN-48-EP(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.50 × 5.50 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L4P5CEU6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L4P5CEU6 (ST, UFQFPN-48-EP(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (49 pins) & STM32L4P5CEU / STM32L4P5VGY / STM32L4P5QGI Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 2 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| 3 | PC14 - OSC32_I N(PC14) | Digital_IO | Signal terminal PC14 - OSC32_I N(PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_I N(PC14). Supported peripheral buses: RTC/CLK. |
| 4 | NC | No_Connect | No Connect (Leave Floating) |
| 5 | PH0-OSC_IN | Digital_IO | Signal terminal PH0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0-OSC_IN. Supported peripheral buses: RTC/CLK. |
| 6 | PH1-OSC_OUT | Digital_IO | Signal terminal PH1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1-OSC_OUT. Supported peripheral buses: RTC/CLK. |
| 7 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 8 | VSSA/VREF- | GND | 0V electrical ground return terminal (VSSA/VREF-) for internal core logic, I/O drivers, and analog sub-blocks. |
| 9 | VDDA/VREF+ | Power_In | Primary positive power supply input (VDDA/VREF+) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 10 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General. |
| 11 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General. |
| 12 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General. |
| 13 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General. |
| 14 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General. |
| 15 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General. |
| 16 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General. |
| 17 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General. |
| 18 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General. |
| 19 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General. |
| 20 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General. |
| 21 | PB10 | Digital_IO | Signal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General. |
| 22 | PB11 | Digital_IO | Signal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General. |
| 23 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 24 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 25 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General. |
| 26 | PB13 | Digital_IO | Signal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General. |
| 27 | PB14 | Digital_IO | Signal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General. |
| 28 | PB15 | Digital_IO | Signal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General. |
| 29 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General. |
| 30 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General. |
| 31 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General. |
| 32 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General. |
| 33 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General. |
| 34 | PA13 | Digital_IO | Signal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General. |
| 35 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 36 | VDDUSB | Power_In | Primary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 37 | PA14 | Digital_IO | Signal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General. |
| 38 | PA15 | Digital_IO | Signal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General. |
| 39 | PB3 | Digital_IO | Signal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General. |
| 40 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General. |
| 41 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General. |
| 42 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General. |
| 43 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General. |
| 44 | PH3-BOOT0 | Digital_IO | Signal terminal PH3-BOOT0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH3-BOOT0. Supported peripheral buses: General. |
| 45 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General. |
| 46 | PB9 | Digital_IO | Signal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General. |
| 47 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 48 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 49 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |