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CH561Q (LQFP-64M(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH561Q

WCHID: C87388LQFP-64M(10x10) · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH561Q (LQFP-64M(10x10))1RSETE2VCC33E3GND4RXP5RXN6VCC18E7TXP8TXN9GND10XI11XO12VCC33U13GND14RSETU15NC16NC17VCC33U18GND19VCC1820GND21VCC3322PB023PB124PB225PB326PB427PB528VCC1829VCC3330PB631PB732PB1664VCC1863VCC3362PB1561PB1460PB1359PB1258PB1157PB1056PB955PB854VCC1853PA1952PA1851PA1750PA1149PA848GND47PA1246PA745VCC3344GND43VCC1842VCC3341GND40VCC33A39AIN038AVRT37GND36RST#35PB1934PB1833PB17Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.245.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=10.00mm · Pitch e=0.50mmD=10.00mm-9-7-5-3-11357997531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RSETEI/OMultiplexed I/O & Peripheral Pin RSETE (General)
2VCC33EPowerPower Supply Input (VCC33E — 3.3V / 5.0V Standard Logic)
3GNDGNDGround Reference Pin (GND)
4RXPI/OMultiplexed I/O & Peripheral Pin RXP (General)
5RXNI/OMultiplexed I/O & Peripheral Pin RXN (General)
6VCC18EPowerPower Supply Input (VCC18E — 3.3V / 5.0V Standard Logic)
7TXPI/OMultiplexed I/O & Peripheral Pin TXP (General)
8TXNI/OMultiplexed I/O & Peripheral Pin TXN (General)
9GNDGNDGround Reference Pin (GND)
10XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
11XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
12VCC33UPowerPower Supply Input (VCC33U — 3.3V / 5.0V Standard Logic)
13GNDGNDGround Reference Pin (GND)
14RSETUI/OMultiplexed I/O & Peripheral Pin RSETU (General)
15NCI/OMultiplexed I/O & Peripheral Pin NC (General)
16NCI/OMultiplexed I/O & Peripheral Pin NC (General)
17VCC33UPowerPower Supply Input (VCC33U — 3.3V / 5.0V Standard Logic)
18GNDGNDGround Reference Pin (GND)
19VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
20GNDGNDGround Reference Pin (GND)
21VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
22PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
23PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
24PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
25PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
26PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
27PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
28VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
29VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
30PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
31PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
32PB16I/OMultiplexed I/O & Peripheral Pin PB16 (General)
33PB17I/OMultiplexed I/O & Peripheral Pin PB17 (General)
34PB18I/OMultiplexed I/O & Peripheral Pin PB18 (General)
35PB19I/OMultiplexed I/O & Peripheral Pin PB19 (General)
36RST#I/OMultiplexed I/O & Peripheral Pin RST# (General)
37GNDGNDGround Reference Pin (GND)
38AVRTI/OMultiplexed I/O & Peripheral Pin AVRT (General)
39AIN0I/OMultiplexed I/O & Peripheral Pin AIN0 (ADC)
40VCC33APowerPower Supply Input (VCC33A — 3.3V / 5.0V Standard Logic)
41GNDGNDGround Reference Pin (GND)
42VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
43VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
44GNDGNDGround Reference Pin (GND)
45VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
46PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
47PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
48GNDGNDGround Reference Pin (GND)
49PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
50PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
51PA17I/OMultiplexed I/O & Peripheral Pin PA17 (General)
52PA18I/OMultiplexed I/O & Peripheral Pin PA18 (General)
53PA19I/OMultiplexed I/O & Peripheral Pin PA19 (General)
54VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
55PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
56PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
57PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
58PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
59PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
60PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
61PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
62PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
63VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
64VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
PIN 1 RSETE
I/O
Multiplexed I/O & Peripheral Pin RSETE (General)
Design note: Signal terminal RSETE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSETE. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH561Q (WCH · LQFP-64M(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH561Q (LQFP-64M(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH561Q (LQFP-64M(10x10)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH561Q (LQFP-64M(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH561Q (LQFP-64M(10x10)) - 4. Package Dimensions (D×E×A)
LQFP-64M(10x10) · 10.00×10.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH561Q (LQFP-64M(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH561Q (LQFP-64M(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (CH561Q)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH561Q (LQFP-64M(10x10)) is a 64-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated ADC, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-64M(10x10))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
ADC, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-64M(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-64M(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH561Q (LQFP-64M(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH561Q (LQFP-64M(10x10))?

Manufactured by WCH, the CH561Q is housed in a LQFP-64M(10x10) package with 64 pins and a 0.50 mm lead pitch. Key pins include: 1 (RSETE: Multiplexed I/O & Peripheral Pin RSETE (General)), 2 (VCC33E: Power Supply Input (VCC33E — 3.3V / 5.0V Standard Logic)), 3 (GND: Ground Reference Pin (GND)), 4 (RXP: Multiplexed I/O & Peripheral Pin RXP (General)), 5 (RXN: Multiplexed I/O & Peripheral Pin RXN (General)), 6 (VCC18E: Power Supply Input (VCC18E — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for CH561Q?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH561Q (LQFP-64M(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH561Q?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH561Q (WCH, LQFP-64M(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & CH561 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RSETEDigital_IOSignal terminal RSETE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSETE. Supported peripheral buses: General.
2VCC33EPower_InPrimary positive power supply input (VCC33E) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
4RXPDigital_IOSignal terminal RXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXP. Supported peripheral buses: General.
5RXNDigital_IOSignal terminal RXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXN. Supported peripheral buses: General.
6VCC18EPower_InPrimary positive power supply input (VCC18E) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
7TXPDigital_IOSignal terminal TXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXP. Supported peripheral buses: General.
8TXNDigital_IOSignal terminal TXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXN. Supported peripheral buses: General.
9GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
10XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
11XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
12VCC33UPower_InPrimary positive power supply input (VCC33U) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
13GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
14RSETUDigital_IOSignal terminal RSETU (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSETU. Supported peripheral buses: General.
15NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
16NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
17VCC33UPower_InPrimary positive power supply input (VCC33U) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
18GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
19VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
20GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
21VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
22PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
23PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
24PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
25PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
26PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
27PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
28VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
29VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
30PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
31PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
32PB16Digital_IOSignal terminal PB16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB16. Supported peripheral buses: General.
33PB17Digital_IOSignal terminal PB17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB17. Supported peripheral buses: General.
34PB18Digital_IOSignal terminal PB18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB18. Supported peripheral buses: General.
35PB19Digital_IOSignal terminal PB19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB19. Supported peripheral buses: General.
36RST#Digital_IOSignal terminal RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General.
37GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
38AVRTDigital_IOSignal terminal AVRT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AVRT. Supported peripheral buses: General.
39AIN0Digital_IOSignal terminal AIN0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AIN0. Supported peripheral buses: ADC.
40VCC33APower_InPrimary positive power supply input (VCC33A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
41GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
42VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
43VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
44GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
45VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
46PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
47PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
48GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
49PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
50PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
51PA17Digital_IOSignal terminal PA17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA17. Supported peripheral buses: General.
52PA18Digital_IOSignal terminal PA18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA18. Supported peripheral buses: General.
53PA19Digital_IOSignal terminal PA19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA19. Supported peripheral buses: General.
54VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
55PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
56PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
57PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
58PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
59PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
60PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
61PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
62PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
63VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
64VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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