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CH563L (LQFP-128(14x14)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH563L

WCHID: C87387LQFP-128(14x14) · 128 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH563L (LQFP-128(14x14))1VCC182GND3RSVD14RSVD05VCC186RSETE7VCC33E8RSVD29GND10RXP11RXN12VCC18E13VCC18E14TXP15TXN16GND17GND18VCC1819XI20XO21VCC33U22GND23RSETU24DN25DP26VCC33U27GND28VCC1829GND30VCC1831PD1632PD1733PD1834PD1935PD2036PD2137PD2238PD2339VCC3340PD2441PD2542PD2643PD2744PD2845PD2946PD3047PD3148PB049PB150PB251PB352PB453PB554VCC1855GND56VCC3357PB658PB759PB1660PB1761PB1862PB1963RST#64GND128PECLP127NC126PD7125PD6124PD5123PD4122VCC33121PD3120PD2119PD1118PD0117PB15116PB14115PB13114PB12113PB11112PB10111PB9110PB8109GND108VCC18107PA21106PA20105PA19104PA18103PA17102PA16101VCC33100PA1199PA1098PA997PA896PA1595PA1494PA1393PA1292P91I/O90I/O89I/O88I/O87I/O86I/O85I/O84I/O83P82P81I/O80I/O79I/O78I/O77I/O76I/O75I/O74I/O73I72P71P70VCC33A69AIN068AIN167AIN266AVRT65AVRBGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.286.481.376.271.166.061.055.950.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8-55.9-61.0-66.0-71.1-76.2-81.3-86.4mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128E=14.00mm · Pitch e=0.40mmD=14.00mm-12-10-8-6-4-2024681012121086420-2-4-6-8-10-12mm
3. 3D CAD MODEL
Package Body: 14.00mm × 14.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (128/128)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
2GNDGNDGround Reference Pin (GND)
3RSVD1I/OMultiplexed I/O & Peripheral Pin RSVD1 (General)
4RSVD0I/OMultiplexed I/O & Peripheral Pin RSVD0 (General)
5VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
6RSETEI/OMultiplexed I/O & Peripheral Pin RSETE (General)
7VCC33EPowerPower Supply Input (VCC33E — 3.3V / 5.0V Standard Logic)
8RSVD2I/OMultiplexed I/O & Peripheral Pin RSVD2 (General)
9GNDGNDGround Reference Pin (GND)
10RXPI/OMultiplexed I/O & Peripheral Pin RXP (General)
11RXNI/OMultiplexed I/O & Peripheral Pin RXN (General)
12VCC18EPowerPower Supply Input (VCC18E — 3.3V / 5.0V Standard Logic)
13VCC18EPowerPower Supply Input (VCC18E — 3.3V / 5.0V Standard Logic)
14TXPI/OMultiplexed I/O & Peripheral Pin TXP (General)
15TXNI/OMultiplexed I/O & Peripheral Pin TXN (General)
16GNDGNDGround Reference Pin (GND)
17GNDGNDGround Reference Pin (GND)
18VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
19XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
20XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
21VCC33UPowerPower Supply Input (VCC33U — 3.3V / 5.0V Standard Logic)
22GNDGNDGround Reference Pin (GND)
23RSETUI/OMultiplexed I/O & Peripheral Pin RSETU (General)
24DNI/OMultiplexed I/O & Peripheral Pin DN (General)
25DPI/OMultiplexed I/O & Peripheral Pin DP (General)
26VCC33UPowerPower Supply Input (VCC33U — 3.3V / 5.0V Standard Logic)
27GNDGNDGround Reference Pin (GND)
28VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
29GNDGNDGround Reference Pin (GND)
30VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
31PD16I/OMultiplexed I/O & Peripheral Pin PD16 (General)
32PD17I/OMultiplexed I/O & Peripheral Pin PD17 (General)
33PD18I/OMultiplexed I/O & Peripheral Pin PD18 (General)
34PD19I/OMultiplexed I/O & Peripheral Pin PD19 (General)
35PD20I/OMultiplexed I/O & Peripheral Pin PD20 (General)
36PD21I/OMultiplexed I/O & Peripheral Pin PD21 (General)
37PD22I/OMultiplexed I/O & Peripheral Pin PD22 (General)
38PD23I/OMultiplexed I/O & Peripheral Pin PD23 (General)
39VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
40PD24I/OMultiplexed I/O & Peripheral Pin PD24 (General)
41PD25I/OMultiplexed I/O & Peripheral Pin PD25 (General)
42PD26I/OMultiplexed I/O & Peripheral Pin PD26 (General)
43PD27I/OMultiplexed I/O & Peripheral Pin PD27 (General)
44PD28I/OMultiplexed I/O & Peripheral Pin PD28 (General)
45PD29I/OMultiplexed I/O & Peripheral Pin PD29 (General)
46PD30I/OMultiplexed I/O & Peripheral Pin PD30 (General)
47PD31I/OMultiplexed I/O & Peripheral Pin PD31 (General)
48PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
49PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
50PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
51PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
52PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
53PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
54VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
55GNDGNDGround Reference Pin (GND)
56VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
57PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
58PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
59PB16I/OMultiplexed I/O & Peripheral Pin PB16 (General)
60PB17I/OMultiplexed I/O & Peripheral Pin PB17 (General)
61PB18I/OMultiplexed I/O & Peripheral Pin PB18 (General)
62PB19I/OMultiplexed I/O & Peripheral Pin PB19 (General)
63RST#I/OMultiplexed I/O & Peripheral Pin RST# (General)
64GNDGNDGround Reference Pin (GND)
65AVRBI/OMultiplexed I/O & Peripheral Pin AVRB (General)
66AVRTI/OMultiplexed I/O & Peripheral Pin AVRT (General)
67AIN2I/OMultiplexed I/O & Peripheral Pin AIN2 (ADC)
68AIN1I/OMultiplexed I/O & Peripheral Pin AIN1 (ADC)
69AIN0I/OMultiplexed I/O & Peripheral Pin AIN0 (ADC)
70VCC33APowerPower Supply Input (VCC33A — 3.3V / 5.0V Standard Logic)
71PI/OMultiplexed I/O & Peripheral Pin P (General)
72PI/OMultiplexed I/O & Peripheral Pin P (General)
73II/OMultiplexed I/O & Peripheral Pin I (General)
74I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
75I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
76I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
77I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
78I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
79I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
80I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
81I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
82PI/OMultiplexed I/O & Peripheral Pin P (General)
83PI/OMultiplexed I/O & Peripheral Pin P (General)
84I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
85I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
86I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
87I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
88I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
89I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
90I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
91I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
92PI/OMultiplexed I/O & Peripheral Pin P (General)
93PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
94PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
95PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
96PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
97PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
98PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
99PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
100PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
101VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
102PA16I/OMultiplexed I/O & Peripheral Pin PA16 (General)
103PA17I/OMultiplexed I/O & Peripheral Pin PA17 (General)
104PA18I/OMultiplexed I/O & Peripheral Pin PA18 (General)
105PA19I/OMultiplexed I/O & Peripheral Pin PA19 (General)
106PA20I/OMultiplexed I/O & Peripheral Pin PA20 (General)
107PA21I/OMultiplexed I/O & Peripheral Pin PA21 (General)
108VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
109GNDGNDGround Reference Pin (GND)
110PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
111PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
112PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
113PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
114PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
115PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
116PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
117PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
118PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
119PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
120PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
121PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
122VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
123PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
124PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
125PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
126PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
127NCI/OMultiplexed I/O & Peripheral Pin NC (General)
128PECLPI/OMultiplexed I/O & Peripheral Pin PECLP (General)
PIN 1 VCC18
Power
Power Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
Design note: VCC18
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH563L (WCH · LQFP-128(14x14))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH563L (LQFP-128(14x14)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH563L (LQFP-128(14x14)) - 2. Standard Pinout (Top View)
True package pinout (128 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH563L (LQFP-128(14x14)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH563L (LQFP-128(14x14)) - 4. Package Dimensions (D×E×A)
LQFP-128(14x14) · 14.00×14.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH563L (LQFP-128(14x14)) - 5. Recommended Land Pattern
IPC-7351B Footprint (128 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH563L (LQFP-128(14x14)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for CH563
P8 · p08_fig01EXACT PACKAGE
CH563L (LQFP-128(14x14)) — 图2-2 LQFP128 封装引脚排列 2.2 引脚描述 管脚号 LQFP128 1 - VCC18 P VCC18 1.8V 内核电源： 内部电路的电源 2 - GND P GND 地： 公共接地端，0V 参考点 3 - RSVD1 保留引脚，禁止连接
图2-2 LQFP128 封装引脚排列 2.2 引脚描述 管脚号 LQFP128 1 - VCC18 P VCC18 1.8V 内核电源： 内部电路的电源 2 - GND P GND 地： 公共接地端，0V 参考点 3 - RSVD1 保留引脚，禁止连接
P8 · p08_fig01P8
CH563L (LQFP-128(14x14)) — Datasheet Page 8 (p08_fig01)
Datasheet Page 8 (p08_fig01)
P18 · p18_fig01737×520px
CH563L (LQFP-128(14x14)) — 4.2.2 外部手工复位
4.2.2 外部手工复位
P54 · p54_fig011713×708px
CH563L (LQFP-128(14x14)) — UARTx_DLL UARTx_DLM [7：0] RW
UARTx_DLL UARTx_DLM [7：0] RW
P54 · p54_fig021713×742px
CH563L (LQFP-128(14x14)) — UART 内置了独立的收发缓冲区及FIFO，支持单工、半双工或者全双工异步串行通讯。串行数据 包括1 个低电平起始位，5、6、7 或8 个数据位，0 个或者1 个附加校验位或者标志位，1 个或者2 个高电平停止位，支持奇校验/偶校验/标志校验/空白校验。支持常用通讯波特率：1200、2400、4800、
UART 内置了独立的收发缓冲区及FIFO，支持单工、半双工或者全双工异步串行通讯。串行数据 包括1 个低电平起始位，5、6、7 或8 个数据位，0 个或者1 个附加校验位或者标志位，1 个或者2 个高电平停止位，支持奇校验/偶校验/标志校验/空白校验。支持常用通讯波特率：1200、2400、4800、
P54 · p54_fig02P54
CH563L (LQFP-128(14x14)) — Datasheet Page 54 (p54_fig02)
Datasheet Page 54 (p54_fig02)
P56 · p56_fig011713×1209px
CH563L (LQFP-128(14x14)) — 32 位宽总线接口：
32 位宽总线接口：
P56 · p56_fig021666×723px
CH563L (LQFP-128(14x14)) — 图9-1 (a) 32 位宽总线接口连接8 位的存储器芯片
图9-1 (a) 32 位宽总线接口连接8 位的存储器芯片
P61 · p61_fig011713×1766px
CH563L (LQFP-128(14x14)) — CH563 芯片的8 位被动并口在使用前，必须先对其进行初始化。 主要配置步骤如下： (1)、配置被动并口配置寄存器(R8_SLV_CONFIG)，设置RB_SLV_ENABLE 位为1 使能被动并口，同 时根据需要设置数据读取、数据输入和命令输入等中断使能。由于此寄存器为写保护寄存器，需要先 对其解锁然后再进行操作；
CH563 芯片的8 位被动并口在使用前，必须先对其进行初始化。 主要配置步骤如下： (1)、配置被动并口配置寄存器(R8_SLV_CONFIG)，设置RB_SLV_ENABLE 位为1 使能被动并口，同 时根据需要设置数据读取、数据输入和命令输入等中断使能。由于此寄存器为写保护寄存器，需要先 对其解锁然后再进行操作；
P7 · p07_fig01All Packages in PDF
CH563L (LQFP-128(14x14)) — 图2-1 LQFP64 封装引脚排列
图2-1 LQFP64 封装引脚排列

Technical Specifications & Part Details (CH563L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH563L (LQFP-128(14x14)) is a 128-pin standard electronic & interconnect component featuring a 14.00 × 14.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, ADC, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
14.00 × 14.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-128(14x14))
Pin Count & Lead PitchN / e
128 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, ADC, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol128 auto-grouped pins
OK
IPC-7351B Land Pattern128 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-128(14x14))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.40mm
Pad Size (W × L)Level B
0.24 × 1.25 mm
Pins / Total PadsTopology
128P / 128Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-128(14x14)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH563L (LQFP-128(14x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH563L (LQFP-128(14x14))?

Manufactured by WCH, the CH563L is housed in a LQFP-128(14x14) package with 128 pins and a 0.40 mm lead pitch. Key pins include: 1 (VCC18: Power Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)), 2 (GND: Ground Reference Pin (GND)), 3 (RSVD1: Multiplexed I/O & Peripheral Pin RSVD1 (General)), 4 (RSVD0: Multiplexed I/O & Peripheral Pin RSVD0 (General)), 5 (VCC18: Power Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)), 6 (RSETE: Multiplexed I/O & Peripheral Pin RSETE (General)).

What are the IPC-7351B PCB Footprint dimensions for CH563L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH563L (LQFP-128(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.40 mm, and 128 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH563L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH563L (WCH, LQFP-128(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (128 pins) & CH563 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3RSVD1Digital_IOSignal terminal RSVD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD1. Supported peripheral buses: General.
4RSVD0Digital_IOSignal terminal RSVD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD0. Supported peripheral buses: General.
5VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6RSETEDigital_IOSignal terminal RSETE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSETE. Supported peripheral buses: General.
7VCC33EPower_InPrimary positive power supply input (VCC33E) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
8RSVD2Digital_IOSignal terminal RSVD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD2. Supported peripheral buses: General.
9GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
10RXPDigital_IOSignal terminal RXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXP. Supported peripheral buses: General.
11RXNDigital_IOSignal terminal RXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXN. Supported peripheral buses: General.
12VCC18EPower_InPrimary positive power supply input (VCC18E) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
13VCC18EPower_InPrimary positive power supply input (VCC18E) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14TXPDigital_IOSignal terminal TXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXP. Supported peripheral buses: General.
15TXNDigital_IOSignal terminal TXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXN. Supported peripheral buses: General.
16GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
17GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
18VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
19XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
20XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
21VCC33UPower_InPrimary positive power supply input (VCC33U) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
22GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
23RSETUDigital_IOSignal terminal RSETU (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSETU. Supported peripheral buses: General.
24DNDigital_IOSignal terminal DN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DN. Supported peripheral buses: General.
25DPDigital_IOSignal terminal DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP. Supported peripheral buses: General.
26VCC33UPower_InPrimary positive power supply input (VCC33U) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
27GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
28VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
29GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
30VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
31PD16Digital_IOSignal terminal PD16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD16. Supported peripheral buses: General.
32PD17Digital_IOSignal terminal PD17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD17. Supported peripheral buses: General.
33PD18Digital_IOSignal terminal PD18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD18. Supported peripheral buses: General.
34PD19Digital_IOSignal terminal PD19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD19. Supported peripheral buses: General.
35PD20Digital_IOSignal terminal PD20 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD20. Supported peripheral buses: General.
36PD21Digital_IOSignal terminal PD21 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD21. Supported peripheral buses: General.
37PD22Digital_IOSignal terminal PD22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD22. Supported peripheral buses: General.
38PD23Digital_IOSignal terminal PD23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD23. Supported peripheral buses: General.
39VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
40PD24Digital_IOSignal terminal PD24 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD24. Supported peripheral buses: General.
41PD25Digital_IOSignal terminal PD25 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD25. Supported peripheral buses: General.
42PD26Digital_IOSignal terminal PD26 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD26. Supported peripheral buses: General.
43PD27Digital_IOSignal terminal PD27 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD27. Supported peripheral buses: General.
44PD28Digital_IOSignal terminal PD28 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD28. Supported peripheral buses: General.
45PD29Digital_IOSignal terminal PD29 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD29. Supported peripheral buses: General.
46PD30Digital_IOSignal terminal PD30 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD30. Supported peripheral buses: General.
47PD31Digital_IOSignal terminal PD31 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD31. Supported peripheral buses: General.
48PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
49PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
50PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
51PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
52PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
53PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
54VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
55GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
56VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
57PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
58PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
59PB16Digital_IOSignal terminal PB16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB16. Supported peripheral buses: General.
60PB17Digital_IOSignal terminal PB17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB17. Supported peripheral buses: General.
61PB18Digital_IOSignal terminal PB18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB18. Supported peripheral buses: General.
62PB19Digital_IOSignal terminal PB19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB19. Supported peripheral buses: General.
63RST#Digital_IOSignal terminal RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General.
64GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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