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AT89C51RC-24AU (TQFP-44(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

AT89C51RC-24AU

MICROCHIPID: C8729TQFP-44(10x10) · 44 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · AT89C51RC-24AU (TQFP-44(10x10))1P1.52P1.63P1.74RST5(RXD) P3.06NIC/27(TXD) P3.18(INT0) P3.29(INT1) P3.310(T0) P3.411(T1) P3.512(WR#) P3.613(RD#) P3.714XTAL215XTAL116VSS17VSS18(A8) P2.019(A9) P2.120(A10) P2.221(A11) P2.322(A12) P2.444P1.443P1.342P1.241P1.1 (T2 EX)40P1.0 (T2)39NIC38VCC37P0.0 (AD0)36P0.1 (AD1)35P0.2 (AD2)34P0.3 (AD3)33P0.4 (AD4)32P0.5 (AD5)31P0.6 (AD6)30P0.7 (AD7)29EA28NIC/427ALE/PROG#26PSEN#25P2.7 (A15)24P2.6 (A14)23P2.5 (A13)Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.833.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344E=10.00mm · Pitch e=0.80mmD=10.00mm-10-8-6-4-202468101086420-2-4-6-8-10mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (44/44)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1P1.5I/OMultiplexed I/O & Peripheral Pin P1.5 (General)
2P1.6I/OMultiplexed I/O & Peripheral Pin P1.6 (General)
3P1.7I/OMultiplexed I/O & Peripheral Pin P1.7 (General)
4RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
5(RXD) P3.0I/OMultiplexed I/O & Peripheral Pin (RXD) P3.0 (UART)
6NIC/2I/OMultiplexed I/O & Peripheral Pin NIC/2 (General)
7(TXD) P3.1I/OMultiplexed I/O & Peripheral Pin (TXD) P3.1 (UART)
8(INT0) P3.2I/OMultiplexed I/O & Peripheral Pin (INT0) P3.2 (General)
9(INT1) P3.3I/OMultiplexed I/O & Peripheral Pin (INT1) P3.3 (General)
10(T0) P3.4I/OMultiplexed I/O & Peripheral Pin (T0) P3.4 (General)
11(T1) P3.5I/OMultiplexed I/O & Peripheral Pin (T1) P3.5 (General)
12(WR#) P3.6I/OMultiplexed I/O & Peripheral Pin (WR#) P3.6 (General)
13(RD#) P3.7I/OMultiplexed I/O & Peripheral Pin (RD#) P3.7 (General)
14XTAL2I/OMultiplexed I/O & Peripheral Pin XTAL2 (RTC/CLK)
15XTAL1I/OMultiplexed I/O & Peripheral Pin XTAL1 (RTC/CLK)
16VSSGNDGround Reference Pin (VSS)
17VSSGNDGround Reference Pin (VSS)
18(A8) P2.0I/OMultiplexed I/O & Peripheral Pin (A8) P2.0 (General)
19(A9) P2.1I/OMultiplexed I/O & Peripheral Pin (A9) P2.1 (General)
20(A10) P2.2I/OMultiplexed I/O & Peripheral Pin (A10) P2.2 (General)
21(A11) P2.3I/OMultiplexed I/O & Peripheral Pin (A11) P2.3 (General)
22(A12) P2.4I/OMultiplexed I/O & Peripheral Pin (A12) P2.4 (General)
23P2.5 (A13)I/OMultiplexed I/O & Peripheral Pin P2.5 (A13) (General)
24P2.6 (A14)I/OMultiplexed I/O & Peripheral Pin P2.6 (A14) (General)
25P2.7 (A15)I/OMultiplexed I/O & Peripheral Pin P2.7 (A15) (General)
26PSEN#I/OMultiplexed I/O & Peripheral Pin PSEN# (General)
27ALE/PROG#I/OMultiplexed I/O & Peripheral Pin ALE/PROG# (General)
28NIC/4I/OMultiplexed I/O & Peripheral Pin NIC/4 (General)
29EAI/OMultiplexed I/O & Peripheral Pin EA (General)
30P0.7 (AD7)I/OMultiplexed I/O & Peripheral Pin P0.7 (AD7) (General)
31P0.6 (AD6)I/OMultiplexed I/O & Peripheral Pin P0.6 (AD6) (General)
32P0.5 (AD5)I/OMultiplexed I/O & Peripheral Pin P0.5 (AD5) (General)
33P0.4 (AD4)I/OMultiplexed I/O & Peripheral Pin P0.4 (AD4) (General)
34P0.3 (AD3)I/OMultiplexed I/O & Peripheral Pin P0.3 (AD3) (General)
35P0.2 (AD2)I/OMultiplexed I/O & Peripheral Pin P0.2 (AD2) (General)
36P0.1 (AD1)I/OMultiplexed I/O & Peripheral Pin P0.1 (AD1) (General)
37P0.0 (AD0)I/OMultiplexed I/O & Peripheral Pin P0.0 (AD0) (General)
38VCCPowerPower Supply Input (VCC — 4V to 5.5V)
39NICI/OMultiplexed I/O & Peripheral Pin NIC (General)
40P1.0 (T2)I/OMultiplexed I/O & Peripheral Pin P1.0 (T2) (General)
41P1.1 (T2 EX)I/OMultiplexed I/O & Peripheral Pin P1.1 (T2 EX) (General)
42P1.2I/OMultiplexed I/O & Peripheral Pin P1.2 (General)
43P1.3I/OMultiplexed I/O & Peripheral Pin P1.3 (General)
44P1.4I/OMultiplexed I/O & Peripheral Pin P1.4 (General)
PIN 1 P1.5
I/O
Multiplexed I/O & Peripheral Pin P1.5 (General)
Design note: Signal terminal P1.5 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P1.5. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: AT89C51RC-24AU (MICROCHIP · TQFP-44(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
AT89C51RC-24AU (TQFP-44(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
AT89C51RC-24AU (TQFP-44(10x10)) - 2. Standard Pinout (Top View)
True package pinout (44 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
AT89C51RC-24AU (TQFP-44(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
AT89C51RC-24AU (TQFP-44(10x10)) - 4. Package Dimensions (D×E×A)
TQFP-44(10x10) · 10.00×10.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
AT89C51RC-24AU (TQFP-44(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (44 Pads)Expand ›
6. Application SchematicSCHEMATIC
AT89C51RC-24AU (TQFP-44(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for AT89C51RC
P2 · p02_fig01EXACT PACKAGE
AT89C51RC-24AU (TQFP-44(10x10)) — 2. Pin Configurations
2. Pin Configurations
P33 · p33_fig01EXACT PACKAGE
AT89C51RC-24AU (TQFP-44(10x10)) — 33 | 1920D-MICRO-6/08 | AT89C51RC | 40. Package Information | 40.1 44A - TQFP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. | 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Prof
33 | 1920D-MICRO-6/08 | AT89C51RC | 40. Package Information | 40.1 44A - TQFP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. | 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Prof
P1 · p01_fig01652×503px
AT89C51RC-24AU (TQFP-44(10x10)) — 8-bit Microcontroller with 32K Bytes Flash
8-bit Microcontroller with 32K Bytes Flash
P2 · p02_fig01P2
AT89C51RC-24AU (TQFP-44(10x10)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P33 · p33_fig01P33
AT89C51RC-24AU (TQFP-44(10x10)) — Datasheet Page 33 (p33_fig01)
Datasheet Page 33 (p33_fig01)
P34 · p34_fig012124×2747px
AT89C51RC-24AU (TQFP-44(10x10)) — 34 | 1920D-MICRO-6/08 AT89C51RC | 40.2 44J - PLCC | A 4.191 - 4.572 | A1 2.286 - 3.048 | A2 0.508 - - | D 17.399 - 17.653 | D1 16.510 - 16.662 Note 2 | E 17.399 - 17.653 | E1 16.510 - 16.662 Note 2 | D2/E2 14.986 - 16.002 | B 0.660 - 0.813
34 | 1920D-MICRO-6/08 AT89C51RC | 40.2 44J - PLCC | A 4.191 - 4.572 | A1 2.286 - 3.048 | A2 0.508 - - | D 17.399 - 17.653 | D1 16.510 - 16.662 Note 2 | E 17.399 - 17.653 | E1 16.510 - 16.662 Note 2 | D2/E2 14.986 - 16.002 | B 0.660 - 0.813
P2 · p02_fig02All Packages in PDF
AT89C51RC-24AU (TQFP-44(10x10)) — 2.3 40P6 - 40-lead PDIP
2.3 40P6 - 40-lead PDIP
P2 · p02_fig03All Packages in PDF
AT89C51RC-24AU (TQFP-44(10x10)) — P1.5 P1.6 P1.7 RST (RXD) P3.0
P1.5 P1.6 P1.7 RST (RXD) P3.0
P35 · p35_fig01All Packages in PDF
AT89C51RC-24AU (TQFP-44(10x10)) — 35 | 1920D-MICRO-6/08 | AT89C51RC | 40.3 40P6 - PDIP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) B 40P6 | 09/28/01 | PIN | 1 | E1 | A1 | B
35 | 1920D-MICRO-6/08 | AT89C51RC | 40.3 40P6 - PDIP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) B 40P6 | 09/28/01 | PIN | 1 | E1 | A1 | B

Technical Specifications & Part Details (AT89C51RC-24AU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:AT89C51RC-24AU (TQFP-44(10x10)) is a 44-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.00 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 4V to 5.5V supply operation across -55°C to +125°C with integrated UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
4V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-55°C to +125°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
33 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.00 mm (A1=0.10 mm)
Package family: TQFP (TQFP-44(10x10))
Pin Count & Lead PitchN / e
44 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol44 auto-grouped pins
OK
IPC-7351B Land Pattern44 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-44(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.80mm
Pad Size (W × L)Level B
0.50 × 1.50 mm
Pins / Total PadsTopology
44P / 44Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TQFP-44(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT89C51RC-24AU (TQFP-44(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT89C51RC-24AU (TQFP-44(10x10))?

Manufactured by MICROCHIP, the AT89C51RC-24AU is housed in a TQFP-44(10x10) package with 44 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 4V to 5.5V. Key pins include: 1 (P1.5: Multiplexed I/O & Peripheral Pin P1.5 (General)), 2 (P1.6: Multiplexed I/O & Peripheral Pin P1.6 (General)), 3 (P1.7: Multiplexed I/O & Peripheral Pin P1.7 (General)), 4 (RST: Multiplexed I/O & Peripheral Pin RST (General)), 5 ((RXD) P3.0: Multiplexed I/O & Peripheral Pin (RXD) P3.0 (UART)), 6 (NIC/2: Multiplexed I/O & Peripheral Pin NIC/2 (General)).

What are the IPC-7351B PCB Footprint dimensions for AT89C51RC-24AU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT89C51RC-24AU (TQFP-44(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 44 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT89C51RC-24AU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT89C51RC-24AU (MICROCHIP, TQFP-44(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (44 pins) & AT89C51RC Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1P1.5Digital_IOSignal terminal P1.5 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P1.5. Supported peripheral buses: General.
2P1.6Digital_IOSignal terminal P1.6 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P1.6. Supported peripheral buses: General.
3P1.7Digital_IOSignal terminal P1.7 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P1.7. Supported peripheral buses: General.
4RSTDigital_IOSignal terminal RST (I/O, 4V to 5.5V domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
5(RXD) P3.0Digital_IOSignal terminal (RXD) P3.0 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: (RXD) P3.0. Supported peripheral buses: UART.
6NIC/2Digital_IOSignal terminal NIC/2 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: NIC/2. Supported peripheral buses: General.
7(TXD) P3.1Digital_IOSignal terminal (TXD) P3.1 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: (TXD) P3.1. Supported peripheral buses: UART.
8(INT0) P3.2Digital_IOSignal terminal (INT0) P3.2 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: (INT0) P3.2. Supported peripheral buses: General.
9(INT1) P3.3Digital_IOSignal terminal (INT1) P3.3 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: (INT1) P3.3. Supported peripheral buses: General.
10(T0) P3.4Digital_IOSignal terminal (T0) P3.4 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: (T0) P3.4. Supported peripheral buses: General.
11(T1) P3.5Digital_IOSignal terminal (T1) P3.5 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: (T1) P3.5. Supported peripheral buses: General.
12(WR#) P3.6Digital_IOSignal terminal (WR#) P3.6 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: (WR#) P3.6. Supported peripheral buses: General.
13(RD#) P3.7Digital_IOSignal terminal (RD#) P3.7 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: (RD#) P3.7. Supported peripheral buses: General.
14XTAL2Digital_IOSignal terminal XTAL2 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: XTAL2. Supported peripheral buses: RTC/CLK.
15XTAL1Digital_IOSignal terminal XTAL1 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: XTAL1. Supported peripheral buses: RTC/CLK.
16VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
18(A8) P2.0Digital_IOSignal terminal (A8) P2.0 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: (A8) P2.0. Supported peripheral buses: General.
19(A9) P2.1Digital_IOSignal terminal (A9) P2.1 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: (A9) P2.1. Supported peripheral buses: General.
20(A10) P2.2Digital_IOSignal terminal (A10) P2.2 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: (A10) P2.2. Supported peripheral buses: General.
21(A11) P2.3Digital_IOSignal terminal (A11) P2.3 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: (A11) P2.3. Supported peripheral buses: General.
22(A12) P2.4Digital_IOSignal terminal (A12) P2.4 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: (A12) P2.4. Supported peripheral buses: General.
23P2.5 (A13)Digital_IOSignal terminal P2.5 (A13) (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P2.5 (A13). Supported peripheral buses: General.
24P2.6 (A14)Digital_IOSignal terminal P2.6 (A14) (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P2.6 (A14). Supported peripheral buses: General.
25P2.7 (A15)Digital_IOSignal terminal P2.7 (A15) (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P2.7 (A15). Supported peripheral buses: General.
26PSEN#Digital_IOSignal terminal PSEN# (I/O, 4V to 5.5V domain). Multiplexed alternate functions: PSEN#. Supported peripheral buses: General.
27ALE/PROG#Digital_IOSignal terminal ALE/PROG# (I/O, 4V to 5.5V domain). Multiplexed alternate functions: ALE/PROG#. Supported peripheral buses: General.
28NIC/4Digital_IOSignal terminal NIC/4 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: NIC/4. Supported peripheral buses: General.
29EADigital_IOSignal terminal EA (I/O, 4V to 5.5V domain). Multiplexed alternate functions: EA. Supported peripheral buses: General.
30P0.7 (AD7)Digital_IOSignal terminal P0.7 (AD7) (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P0.7 (AD7). Supported peripheral buses: General.
31P0.6 (AD6)Digital_IOSignal terminal P0.6 (AD6) (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P0.6 (AD6). Supported peripheral buses: General.
32P0.5 (AD5)Digital_IOSignal terminal P0.5 (AD5) (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P0.5 (AD5). Supported peripheral buses: General.
33P0.4 (AD4)Digital_IOSignal terminal P0.4 (AD4) (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P0.4 (AD4). Supported peripheral buses: General.
34P0.3 (AD3)Digital_IOSignal terminal P0.3 (AD3) (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P0.3 (AD3). Supported peripheral buses: General.
35P0.2 (AD2)Digital_IOSignal terminal P0.2 (AD2) (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P0.2 (AD2). Supported peripheral buses: General.
36P0.1 (AD1)Digital_IOSignal terminal P0.1 (AD1) (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P0.1 (AD1). Supported peripheral buses: General.
37P0.0 (AD0)Digital_IOSignal terminal P0.0 (AD0) (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P0.0 (AD0). Supported peripheral buses: General.
38VCCPower_InPrimary positive power supply input (VCC) operating in the 4V to 5.5V domain (Max rating: 5.5V).
39NICDigital_IOSignal terminal NIC (I/O, 4V to 5.5V domain). Multiplexed alternate functions: NIC. Supported peripheral buses: General.
40P1.0 (T2)Digital_IOSignal terminal P1.0 (T2) (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P1.0 (T2). Supported peripheral buses: General.
41P1.1 (T2 EX)Digital_IOSignal terminal P1.1 (T2 EX) (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P1.1 (T2 EX). Supported peripheral buses: General.
42P1.2Digital_IOSignal terminal P1.2 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P1.2. Supported peripheral buses: General.
43P1.3Digital_IOSignal terminal P1.3 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P1.3. Supported peripheral buses: General.
44P1.4Digital_IOSignal terminal P1.4 (I/O, 4V to 5.5V domain). Multiplexed alternate functions: P1.4. Supported peripheral buses: General.
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