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SOP-8 · 8P
Synchronized Pinout (Symbol / 2D / 3D) (16/16)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | GND | GND | Ground Reference Pin (GND) |
| 2 | TXD | I/O | Multiplexed I/O & Peripheral Pin TXD (UART) |
| 3 | RXD | I/O | Multiplexed I/O & Peripheral Pin RXD (UART) |
| 4 | V3 | Power | Internal 3.3V USB Transceiver Supply / LDO Bypass (V3) |
| 5 | UD+ | I/O | Multiplexed I/O & Peripheral Pin UD+ (USB) |
| 6 | UD- | I/O | Multiplexed I/O & Peripheral Pin UD- (USB) |
| 7 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (RTC/CLK) |
| 8 | OUT# | I/O | Multiplexed I/O & Peripheral Pin OUT# (RTC/CLK) |
| 9 | CTS# | I/O | Multiplexed I/O & Peripheral Pin CTS# (UART) |
| 10 | DSR# | I/O | Multiplexed I/O & Peripheral Pin DSR# (UART) |
| 11 | RI# | I/O | Multiplexed I/O & Peripheral Pin RI# (General) |
| 12 | DCD# | I/O | Multiplexed I/O & Peripheral Pin DCD# (General) |
| 13 | DTR# | I/O | Multiplexed I/O & Peripheral Pin DTR# (UART) |
| 14 | RTS# | I/O | Multiplexed I/O & Peripheral Pin RTS# (UART) |
| 15 | R232 | I/O | Multiplexed I/O & Peripheral Pin R232 (UART) |
| 16 | VCC | Power | Power Supply Input (VCC — 3.3V / 5.0V USB-UART Domain) |
PIN 1 GND
GNDGround Reference Pin (GND)
Design note: Public Ground reference (connect directly to USB Shield/GND plane)
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (16 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SOP-16 · 3.90×9.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (16 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for CH340
P2 · p02_fig01EXACT PACKAGE
P1 · p01_fig011549×473px
P2 · p02_fig02P2
P3 · p03_fig01P3
P12 · p12_fig011115×531px
P12 · p12_fig01P12
P15 · p15_fig01P15
P15 · p15_fig02P15
P12 · p12_fig02All Packages in PDF
P13 · p13_fig01All Packages in PDF
P14 · p14_fig01All Packages in PDF
P1 · p01_fig02All Packages in PDF
Page 1 / 2 (13 extracted figures)
Technical Specifications & Part Details (CH340C)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH340C (SOP-16) is a 16-pin interface bridge / precision clock & timer ic featuring a 9.90 × 3.90 × 1.75 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 3.3V / 5.0V Dual-Mode supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.3V / 5.0V Dual-Mode
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
12MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
9 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
9.90 × 3.90 × 1.75 mm (A1=0.00 mm)
Package family: SOP (SOP-16)
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol16 auto-grouped pins
IPC-7351B Land Pattern16 pads · Pitch 1.27mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH340 (7)
MSOP-10 · 10P
MSOP-10 · 10P
ESSOP-10-150mil-1mm · 11P
SOP-16 · 16P
SOP-16 · 16P
SOP-28-300mil · 28P
Mechanical Dimensions & Land Pattern (SOP-16)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
9.90 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.75mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.55 mm
Pins / Total PadsTopology
16P / 16Pad (DUAL_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| C1 BOM | 100nF (0.1µF) 50V X7R 0402 / 0603 | Internal 3.3V LDO cap at V3 (Pin 4) — to GND at VCC=5V, or tie V3 directly to VCC at 3.3V. |
| C2, C3 BOM | 100nF + 10µF 0603 | Main VCC supply decoupling (Pin 16) from USB VBUS — place < 2mm from Pin 16. |
| CH340C WCH | 100% Drop-in | 100% Pin-to-Pin SOP-16 (Built-in 12MHz clock) — shares SOP-16 PCB footprint with CH340G; leave Y1/22pF DNI. |
| CH340G WCH | 100% Drop-in | 100% Pin-to-Pin SOP-16 — requires external 12MHz crystal + two 22pF load caps on Pins 7-8. |
| CH340B WCH | 100% Drop-in | 100% Pin-to-Pin SOP-16 (Built-in 12MHz clock) — shares SOP-16 PCB footprint with CH340G; leave Y1/22pF DNI. |
Technical Frequently Asked Questions (FAQ) — CH340C (SOP-16)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH340C (SOP-16)?
Manufactured by WCH, the CH340C is housed in a SOP-16 package with 16 pins and a 1.27 mm lead pitch. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (TXD: Multiplexed I/O & Peripheral Pin TXD (UART)), 3 (RXD: Multiplexed I/O & Peripheral Pin RXD (UART)), 4 (V3: Internal 3.3V USB Transceiver Supply / LDO Bypass (V3)), 5 (UD+: Multiplexed I/O & Peripheral Pin UD+ (USB)), 6 (UD-: Multiplexed I/O & Peripheral Pin UD- (USB)).
What are the IPC-7351B PCB Footprint dimensions for CH340C?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH340C (SOP-16) has a nominal body envelope of 3.90 × 9.90 mm, pitch e = 1.27 mm, and 16 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH340C?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH340C (WCH, SOP-16) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (16 pins) & CH340 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 2 | TXD | Digital_IO | Signal terminal TXD (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: UART_TXD. Supported peripheral buses: UART. |
| 3 | RXD | Digital_IO | Signal terminal RXD (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: UART_RXD. Supported peripheral buses: UART. |
| 4 | V3 | Power_Out | Internal 3.3V LDO regulator node supplying the USB transceiver and clock generator. |
| 5 | UD+ | Digital_IO | Signal terminal UD+ (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: USB_DP. Supported peripheral buses: USB. |
| 6 | UD- | Digital_IO | Signal terminal UD- (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: USB_DM. Supported peripheral buses: USB. |
| 7 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: XTAL_IN, NC. Supported peripheral buses: RTC/CLK. |
| 8 | OUT# | Analog | Signal terminal OUT# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: XTAL_OUT. Supported peripheral buses: RTC/CLK. |
| 9 | CTS# | Digital_IO | Signal terminal CTS# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: MODEM_CTS. Supported peripheral buses: UART. |
| 10 | DSR# | Digital_IO | Signal terminal DSR# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: MODEM_DSR. Supported peripheral buses: UART. |
| 11 | RI# | Digital_IO | Signal terminal RI# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: MODEM_RI. Supported peripheral buses: General. |
| 12 | DCD# | Digital_IO | Signal terminal DCD# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: MODEM_DCD. Supported peripheral buses: General. |
| 13 | DTR# | Digital_IO | Signal terminal DTR# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: MODEM_DTR, AUTO_ISP_RESET. Supported peripheral buses: UART. |
| 14 | RTS# | Digital_IO | Signal terminal RTS# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: MODEM_RTS, AUTO_ISP_BOOT. Supported peripheral buses: UART. |
| 15 | R232 | Digital_IO | Signal terminal R232 (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: RS232_ENABLE. Supported peripheral buses: UART. |
| 16 | VCC | Power_In | Primary positive power supply input (VCC) operating in the 3.3V / 5.0V USB-UART Domain domain (Max rating: 5.5V). |