STM32F103C6T6A (LQFP-48(7x7)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of STM32F103C6T6A (LQFP-48(7x7))?

Manufactured by ST, the STM32F103C6T6A is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (PC14-OSC32_IN: Multiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)), 4 (PC15-OSC32_OUT: Multiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)), 5 (PD0-OSC_IN: Multiplexed I/O & Peripheral Pin PD0-OSC_IN (RTC/CLK)), 6 (PD1-OSC_OUT: Multiplexed I/O & Peripheral Pin PD1-OSC_OUT (RTC/CLK)).

Q: What are the IPC-7351B PCB Footprint dimensions for STM32F103C6T6A?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F103C6T6A (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F103C6T6A?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F103C6T6A (ST, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	VBAT	Power	Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))
2	PC13	I/O	Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
3	PC14-OSC32_IN	I/O	Multiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
4	PC15-OSC32_OUT	I/O	Multiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
5	PD0-OSC_IN	I/O	Multiplexed I/O & Peripheral Pin PD0-OSC_IN (RTC/CLK)
6	PD1-OSC_OUT	I/O	Multiplexed I/O & Peripheral Pin PD1-OSC_OUT (RTC/CLK)
7	NRST	I	System Enable & Hardware Reset (NRST)
8	VSSA	GND	Ground Reference Pin (VSSA)
9	VDDA	Power	Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))
10	PA0-WKUP	I/O	Multiplexed I/O & Peripheral Pin PA0-WKUP (UART, ADC, PWM)
11	PA1	I/O	Multiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
12	PA2	I/O	Multiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
13	PA3	I/O	Multiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
14	PA4	I/O	Multiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
15	PA5	I/O	Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
16	PA6	I/O	Multiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
17	PA7	I/O	Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
18	PB0	I/O	Multiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
19	PB1	I/O	Multiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
20	PB2/BOOT1	I/O	Multiplexed I/O & Peripheral Pin PB2/BOOT1 (General)
21	PB10	I/O	Multiplexed I/O & Peripheral Pin PB10 (UART, I2C, PWM)
22	PB11	I/O	Multiplexed I/O & Peripheral Pin PB11 (UART, I2C, PWM)
23	VSS_1	GND	Ground Reference Pin (VSS_1)
24	VDD_1	Power	Power Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
25	PB12	I/O	Multiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
26	PB13	I/O	Multiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
27	PB14	I/O	Multiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
28	PB15	I/O	Multiplexed I/O & Peripheral Pin PB15 (SPI, PWM)
29	PA8	I/O	Multiplexed I/O & Peripheral Pin PA8 (UART, PWM, RTC/CLK)
30	PA9	I/O	Multiplexed I/O & Peripheral Pin PA9 (UART, PWM)
31	PA10	I/O	Multiplexed I/O & Peripheral Pin PA10 (UART, PWM)
32	PA11	I/O	Multiplexed I/O & Peripheral Pin PA11 (USB, UART, PWM, CAN)
33	PA12	I/O	Multiplexed I/O & Peripheral Pin PA12 (USB, UART, CAN)
34	PA13	I/O	Multiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
35	VSS_2	GND	Ground Reference Pin (VSS_2)
36	VDD_2	Power	Power Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
37	PA14	I/O	Multiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
38	PA15	I/O	Multiplexed I/O & Peripheral Pin PA15 (SPI, PWM, SWD/JTAG)
39	PB3	I/O	Multiplexed I/O & Peripheral Pin PB3 (SPI, PWM, SWD/JTAG)
40	PB4	I/O	Multiplexed I/O & Peripheral Pin PB4 (SPI, PWM, SWD/JTAG)
41	PB5	I/O	Multiplexed I/O & Peripheral Pin PB5 (SPI, I2C, PWM)
42	PB6	I/O	Multiplexed I/O & Peripheral Pin PB6 (UART, I2C, PWM)
43	PB7	I/O	Multiplexed I/O & Peripheral Pin PB7 (UART, I2C, PWM)
44	BOOT0	I	Input-Only Pin BOOT0 (General)
45	PB8	I/O	Multiplexed I/O & Peripheral Pin PB8 (I2C, PWM, CAN)
46	PB9	I/O	Multiplexed I/O & Peripheral Pin PB9 (I2C, PWM, CAN)
47	VSS_3	GND	Ground Reference Pin (VSS_3)
48	VDD_3	Power	Power Supply Input (VDD_3 — 3.3V VDD (Max 4.0V))

PIN 1 VBAT

Power

Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))

Design note: Backup power supply for RTC and backup registers (1.8V ~ 3.6V)

IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 17 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

Open PDF in New Window ↗Read Datasheet PDF (.pdf)

PDF VIEWEROfficial Datasheet Document: STM32F103C6T6A (ST · LQFP-48(7x7))

Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below

1. Realistic 3D PackageREPRESENTATIVE

STM32F103C6T6A (LQFP-48(7x7)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

STM32F103C6T6A (LQFP-48(7x7)) - 2. Standard Pinout (Top View)

True package pinout (48 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

STM32F103C6T6A (LQFP-48(7x7)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

STM32F103C6T6A (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)

LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

STM32F103C6T6A (LQFP-48(7x7)) - 5. Recommended Land Pattern

IPC-7351B Footprint (48 Pads)Expand ›

6. Application SchematicSCHEMATIC

STM32F103C6T6A (LQFP-48(7x7)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (17 figures · Page 1/2)

Showing 1–12 of 17 uncropped original figures for STM32F103

P23 · p23_fig01EXACT PACKAGE

Figure 5. STM32F103xx performance line LQFP48 pinout

P82 · p82_fig01EXACT PACKAGE

Figure 46. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline(1)

P1 · p01_fig01881×713px

STM32F103x4 STM32F103x6 Low-density performance line, ARM-based 32-bit MCU with 16 or

P1 · p01_fig02886×522px

May 2013 Doc ID 15060 Rev 6 1/90

P23 · p23_fig021546×907px

Figure 6. STM32F103xx performance line UFQFPN48 pinout

P23 · p23_fig01P23

Datasheet Page 23 (p23_fig01)

P30 · p30_fig011747×702px

Figure 9. Pin loading conditions Figure 10. Pin input voltage

P30 · p30_fig021546×1237px

Figure 11. Power supply scheme

P30 · p30_fig01P30

Datasheet Page 30 (p30_fig01)

P47 · p47_fig011546×513px

Figure 21. Typical application with an 8 MHz crystal

P49 · p49_fig011751×732px

Figure 22. Typical application with a 32.768 kHz crystal

P77 · p77_fig011546×1434px

Figure 40. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline 0ININDENTIFIER LASERMARKINGAREA

Page 1 / 2 (17 extracted figures)

Technical Specifications & Part Details (STM32F103C6T6A)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Embedded Microcontroller Unit (MCU)

Detailed Overview:STM32F103C6T6A (LQFP-48(7x7)) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG interfaces.

Operating Supply VoltageV_CC / V_DD

3.0V ~ 3.6V (Typ 3.3V)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

72 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

21 5V-tolerant (FT) pins detected

Package Envelope (D × E × A)D × E × A

7.00 × 7.00 × 1.60 mm (A1=0.10 mm)

Package family: LQFP (LQFP-48(7x7))

Pin Count & Lead PitchN / e

48 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, UART, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Boot Strapping Pin Alert (PB2/BOOT1, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol48 auto-grouped pins

IPC-7351B Land Pattern48 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

7.00 × 7.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.60mm · e=0.50mm

Pad Size (W × L)Level B

0.28 × 1.25 mm

Pins / Total PadsTopology

48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
C1, C2, C3 BOM	3× 100nF (0.1µF) 50V X7R 0402 / 0603	Digital supply decoupling caps for VDD_1..3 (Pins 24, 36, 48) — place < 1.5mm from each VDD pin.
C4 BOM	4.7µF ~ 10µF 10V X5R 0603 / 0805	Bulk decoupling capacitor for main VDD rail — place near 3.3V power entry to the MCU.
C5, C6 + FB1 BOM	100nF + 1µF + Ferrite 600Ω@100MHz 0402 / 0603	Analog rail filter for VDDA/VSSA (Pins 8, 9) 12-bit ADC — isolate digital switching noise.
Y1 + C7, C8 BOM	8MHz Crystal (CL=12pF) + 2× 18pF NP0 SMD-3225 + 0402	Main HSE oscillator crystal (Pin 5 PD0, Pin 6 PD1) — route matched traces < 4mm with GND guard ring.
STM32F103CBT6 STMicroelectronics	100% Drop-in (128KB Flash Upgrade)	100% Drop-in (128KB Flash Upgrade) — identical LQFP-48 pinout with doubled Flash capacity.
GD32F103C8T6 GigaDevice	Pin-to-Pin LQFP-48 (108MHz)	Pin-to-Pin LQFP-48 (108MHz) — higher core clock; verify Flash wait-states & USB timing.
APM32F103C8T6 Geehy	Pin-to-Pin LQFP-48 (96MHz)	Pin-to-Pin LQFP-48 (96MHz) — direct hardware replacement, register-compatible with STM32F1.

Technical Frequently Asked Questions (FAQ) — STM32F103C6T6A (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F103C6T6A (LQFP-48(7x7))?

Manufactured by ST, the STM32F103C6T6A is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (PC14-OSC32_IN: Multiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)), 4 (PC15-OSC32_OUT: Multiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)), 5 (PD0-OSC_IN: Multiplexed I/O & Peripheral Pin PD0-OSC_IN (RTC/CLK)), 6 (PD1-OSC_OUT: Multiplexed I/O & Peripheral Pin PD1-OSC_OUT (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32F103C6T6A?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F103C6T6A (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F103C6T6A?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F103C6T6A (ST, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & STM32F103 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	VBAT	Power_In	Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2	PC13	Digital_IO	Signal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: TAMPER-RTC, RTC_OUT, RTC_CALIB. Supported peripheral buses: RTC/CLK.
3	PC14-OSC32_IN	Digital_IO	Signal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC32_IN, PC14. Supported peripheral buses: RTC/CLK.
4	PC15-OSC32_OUT	Digital_IO	Signal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC32_OUT, PC15. Supported peripheral buses: RTC/CLK.
5	PD0-OSC_IN	Digital_IO	Signal terminal PD0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN, PD0. Supported peripheral buses: RTC/CLK.
6	PD1-OSC_OUT	Digital_IO	Signal terminal PD1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT, PD1. Supported peripheral buses: RTC/CLK.
7	NRST	Digital_IO	Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8	VSSA	GND	0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
9	VDDA	Power_In	Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
10	PA0-WKUP	Analog	Signal terminal PA0-WKUP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: WKUP, USART2_CTS, ADC12_IN0, TIM2_CH1_ETR. Supported peripheral buses: UART, ADC, PWM.
11	PA1	Analog	Signal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USART2_RTS, ADC12_IN1, TIM2_CH2. Supported peripheral buses: UART, ADC, PWM.
12	PA2	Analog	Signal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USART2_TX, ADC12_IN2, TIM2_CH3. Supported peripheral buses: UART, ADC, PWM.
13	PA3	Analog	Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USART2_RX, ADC12_IN3, TIM2_CH4. Supported peripheral buses: UART, ADC, PWM.
14	PA4	Analog	Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, USART2_CK, ADC12_IN4. Supported peripheral buses: UART, SPI, ADC.
15	PA5	Analog	Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK, ADC12_IN5. Supported peripheral buses: SPI, ADC.
16	PA6	Analog	Signal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO, ADC12_IN6, TIM3_CH1, TIM1_BKIN. Supported peripheral buses: SPI, ADC, PWM.
17	PA7	Analog	Signal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI, ADC12_IN7, TIM3_CH2, TIM1_CH1N. Supported peripheral buses: SPI, ADC, PWM.
18	PB0	Analog	Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: ADC12_IN8, TIM3_CH3, TIM1_CH2N. Supported peripheral buses: ADC, PWM.
19	PB1	Analog	Signal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: ADC12_IN9, TIM3_CH4, TIM1_CH3N. Supported peripheral buses: ADC, PWM.
20	PB2/BOOT1	Digital_IO	Signal terminal PB2/BOOT1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: BOOT1, PB2. Supported peripheral buses: General.
21	PB10	Digital_IO	Signal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL, USART3_TX, TIM2_CH3. Supported peripheral buses: UART, I2C, PWM.
22	PB11	Digital_IO	Signal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA, USART3_RX, TIM2_CH4. Supported peripheral buses: UART, I2C, PWM.
23	VSS_1	GND	0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks.
24	VDD_1	Power_In	Primary positive power supply input (VDD_1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
25	PB12	Digital_IO	Signal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, I2C2_SMBA, USART3_CK, TIM1_BKIN. Supported peripheral buses: UART, SPI, I2C.
26	PB13	Digital_IO	Signal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK, USART3_CTS, TIM1_CH1N. Supported peripheral buses: UART, SPI, PWM.
27	PB14	Digital_IO	Signal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO, USART3_RTS, TIM1_CH2N. Supported peripheral buses: UART, SPI, PWM.
28	PB15	Digital_IO	Signal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI, TIM1_CH3N. Supported peripheral buses: SPI, PWM.
29	PA8	Digital_IO	Signal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USART1_CK, TIM1_CH1, MCO. Supported peripheral buses: UART, PWM, RTC/CLK.
30	PA9	Digital_IO	Signal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USART1_TX, TIM1_CH2. Supported peripheral buses: UART, PWM.
31	PA10	Digital_IO	Signal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USART1_RX, TIM1_CH3. Supported peripheral buses: UART, PWM.
32	PA11	Digital_IO	Signal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USB_DM, CAN_RX, USART1_CTS, TIM1_CH4. Supported peripheral buses: USB, UART, PWM, CAN.
33	PA12	Digital_IO	Signal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: USB_DP, CAN_TX, USART1_RTS, TIM1_ETR. Supported peripheral buses: USB, UART, CAN.
34	PA13	Digital_IO	Signal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTMS, SWDIO. Supported peripheral buses: SWD/JTAG.
35	VSS_2	GND	0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks.
36	VDD_2	Power_In	Primary positive power supply input (VDD_2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
37	PA14	Digital_IO	Signal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTCK, SWCLK. Supported peripheral buses: SWD/JTAG.
38	PA15	Digital_IO	Signal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTDI, SPI1_NSS, TIM2_CH1_ETR. Supported peripheral buses: SPI, PWM, SWD/JTAG.
39	PB3	Digital_IO	Signal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTDO, SPI1_SCK, TIM2_CH2, TRACESWO. Supported peripheral buses: SPI, PWM, SWD/JTAG.
40	PB4	Digital_IO	Signal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: NJTRST, SPI1_MISO, TIM3_CH1. Supported peripheral buses: SPI, PWM, SWD/JTAG.
41	PB5	Digital_IO	Signal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSI, TIM3_CH2. Supported peripheral buses: SPI, I2C, PWM.
42	PB6	Digital_IO	Signal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL, TIM4_CH1, USART1_TX. Supported peripheral buses: UART, I2C, PWM.
43	PB7	Digital_IO	Signal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA, TIM4_CH2, USART1_RX. Supported peripheral buses: UART, I2C, PWM.
44	BOOT0	Digital_IO	Signal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
45	PB8	Digital_IO	Signal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: TIM4_CH3, I2C1_SCL, CAN_RX. Supported peripheral buses: I2C, PWM, CAN.
46	PB9	Digital_IO	Signal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: TIM4_CH4, I2C1_SDA, CAN_TX. Supported peripheral buses: I2C, PWM, CAN.
47	VSS_3	GND	0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
48	VDD_3	Power_In	Primary positive power supply input (VDD_3) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).

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