ChipDocs.org
⌘K
2284 PARTSUpload PDF
PIC16F877-20I/L (PLCC-44(16.6x16.6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC16F877-20I/L

MICROCHIPID: C8236PLCC-44(16.6x16.6) · 44 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC16F877-20I/L (PLCC-44(16.6x16.6))1NC2MCLR/VPP3RA0/AN04RA1/AN15RA2/AN2/VREF6RA3/AN3/VREF7RA4/T0CKI8RA5/AN4/SS9RE0/AN5/RD10RE1/AN6/WR11RE2/AN7/CS12VDD13VSS14OSC1/CLKIN15OSC2/CLKOUT16RC0/T1OSO/T117NC18STATUS19OPTION_REG20INTCON21PIE122PIR144RB7/PGD43RB6/PGC42EECON141EECON240NC39RB3/PGM38RB237TRISE36PORTE35TRISD34VSS33TRISC32RD6/PSP631TRISB30RD4/PSP429TRISA28NC27FSR26PCLATH25PCON24PIR223PIE2Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.833.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344E=16.60mm · Pitch e=1.27mmD=16.60mm-15-13-11-9-7-5-3-11357911131515131197531-1-3-5-7-9-11-13-15mm
3. 3D CAD MODEL
Package Body: 16.60mm × 16.60mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (44/44)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1NCI/OMultiplexed I/O & Peripheral Pin NC (General)
2MCLR/VPPI/OMultiplexed I/O & Peripheral Pin MCLR/VPP (General)
3RA0/AN0I/OMultiplexed I/O & Peripheral Pin RA0/AN0 (General)
4RA1/AN1I/OMultiplexed I/O & Peripheral Pin RA1/AN1 (General)
5RA2/AN2/VREF-AnalogMultiplexed I/O & Peripheral Pin RA2/AN2/VREF- (General)
6RA3/AN3/VREF+AnalogMultiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)
7RA4/T0CKII/OMultiplexed I/O & Peripheral Pin RA4/T0CKI (General)
8RA5/AN4/SSI/OMultiplexed I/O & Peripheral Pin RA5/AN4/SS (General)
9RE0/AN5/RDI/OMultiplexed I/O & Peripheral Pin RE0/AN5/RD (General)
10RE1/AN6/WRI/OMultiplexed I/O & Peripheral Pin RE1/AN6/WR (General)
11RE2/AN7/CSI/OMultiplexed I/O & Peripheral Pin RE2/AN7/CS (General)
12VDDPowerPower Supply Input (VDD — 2.0V to 5.5V)
13VSSGNDGround Reference Pin (VSS)
14OSC1/CLKINI/OMultiplexed I/O & Peripheral Pin OSC1/CLKIN (RTC/CLK)
15OSC2/CLKOUTI/OMultiplexed I/O & Peripheral Pin OSC2/CLKOUT (RTC/CLK)
16RC0/T1OSO/T1CKII/OMultiplexed I/O & Peripheral Pin RC0/T1OSO/T1CKI (General)
17NCI/OMultiplexed I/O & Peripheral Pin NC (General)
18STATUSI/OMultiplexed I/O & Peripheral Pin STATUS (General)
19OPTION_REGI/OMultiplexed I/O & Peripheral Pin OPTION_REG (General)
20INTCONI/OMultiplexed I/O & Peripheral Pin INTCON (General)
21PIE1I/OMultiplexed I/O & Peripheral Pin PIE1 (General)
22PIR1I/OMultiplexed I/O & Peripheral Pin PIR1 (General)
23PIE2I/OMultiplexed I/O & Peripheral Pin PIE2 (General)
24PIR2I/OMultiplexed I/O & Peripheral Pin PIR2 (General)
25PCONI/OMultiplexed I/O & Peripheral Pin PCON (General)
26PCLATHI/OMultiplexed I/O & Peripheral Pin PCLATH (General)
27FSRI/OMultiplexed I/O & Peripheral Pin FSR (General)
28NCI/OMultiplexed I/O & Peripheral Pin NC (General)
29TRISAI/OMultiplexed I/O & Peripheral Pin TRISA (General)
30RD4/PSP4I/OMultiplexed I/O & Peripheral Pin RD4/PSP4 (General)
31TRISBI/OMultiplexed I/O & Peripheral Pin TRISB (General)
32RD6/PSP6I/OMultiplexed I/O & Peripheral Pin RD6/PSP6 (General)
33TRISCI/OMultiplexed I/O & Peripheral Pin TRISC (General)
34VSSGNDGround Reference Pin (VSS)
35TRISDI/OMultiplexed I/O & Peripheral Pin TRISD (General)
36PORTEI/OMultiplexed I/O & Peripheral Pin PORTE (General)
37TRISEI/OMultiplexed I/O & Peripheral Pin TRISE (General)
38RB2I/OMultiplexed I/O & Peripheral Pin RB2 (General)
39RB3/PGMI/OMultiplexed I/O & Peripheral Pin RB3/PGM (General)
40NCI/OMultiplexed I/O & Peripheral Pin NC (General)
41EECON2I/OMultiplexed I/O & Peripheral Pin EECON2 (General)
42EECON1I/OMultiplexed I/O & Peripheral Pin EECON1 (General)
43RB6/PGCI/OMultiplexed I/O & Peripheral Pin RB6/PGC (General)
44RB7/PGDI/OMultiplexed I/O & Peripheral Pin RB7/PGD (General)
PIN 1 NC
I/O
Multiplexed I/O & Peripheral Pin NC (General)
Design note: Thesepinsarenotinternallyconnected Thesepins . shouldbeleftunconnected .
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC16F877-20I/L (MICROCHIP · PLCC-44(16.6x16.6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC16F877-20I/L (PLCC-44(16.6x16.6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC16F877-20I/L (PLCC-44(16.6x16.6)) - 2. Standard Pinout (Top View)
True package pinout (44 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC16F877-20I/L (PLCC-44(16.6x16.6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC16F877-20I/L (PLCC-44(16.6x16.6)) - 4. Package Dimensions (D×E×A)
PLCC-44(16.6x16.6) · 16.60×16.60mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC16F877-20I/L (PLCC-44(16.6x16.6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (44 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC16F877-20I/L (PLCC-44(16.6x16.6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for PIC16F877
P1 · p01_fig01867×1053px
PIC16F877-20I/L (PLCC-44(16.6x16.6)) — 28/40-Pin 8-Bit CMOS FLASH Microcontrollers
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
P1 · p01_fig01P1
PIC16F877-20I/L (PLCC-44(16.6x16.6)) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P2 · p02_fig01834×893px
PIC16F877-20I/L (PLCC-44(16.6x16.6)) — PLCC
PLCC
P2 · p02_fig021149×890px
PIC16F877-20I/L (PLCC-44(16.6x16.6)) — RC2/CCP1 RC3/SCK/SCL
RC2/CCP1 RC3/SCK/SCL
P2 · p02_fig03852×894px
PIC16F877-20I/L (PLCC-44(16.6x16.6)) — DS30292D-page 2  1998-2013 Microchip Technology Inc.
DS30292D-page 2  1998-2013 Microchip Technology Inc.
P59 · p59_fig01867×515px
PIC16F877-20I/L (PLCC-44(16.6x16.6)) — FIGURE 8-1: CAPTURE MODE OPERATION BLOCK DIAGRAM RC2/CCP1
FIGURE 8-1: CAPTURE MODE OPERATION BLOCK DIAGRAM RC2/CCP1
P60 · p60_fig01867×699px
PIC16F877-20I/L (PLCC-44(16.6x16.6)) — FIGURE 8-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>).
FIGURE 8-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>).
P134 · p134_fig01869×1162px
PIC16F877-20I/L (PLCC-44(16.6x16.6)) — Note 1: The High Voltage Programming mode is | always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. | 2: While in Low Voltage ICSP mode, the RB3 pin can no longer be used as a gen- eral purpose I/O pin
Note 1: The High Voltage Programming mode is | always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. | 2: While in Low Voltage ICSP mode, the RB3 pin can no longer be used as a gen- eral purpose I/O pin
P135 · p135_fig011778×1499px
PIC16F877-20I/L (PLCC-44(16.6x16.6)) — FIGURE 13-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 0
FIGURE 13-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 0
P189 · p189_fig021777×871px
PIC16F877-20I/L (PLCC-44(16.6x16.6)) —  1998-2013 Microchip Technology Inc. DS30292D-page 189 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for custome
 1998-2013 Microchip Technology Inc. DS30292D-page 189 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for custome
P189 · p189_fig02P189
PIC16F877-20I/L (PLCC-44(16.6x16.6)) — Datasheet Page 189 (p189_fig02)
Datasheet Page 189 (p189_fig02)
P195 · p195_fig011442×1778px
PIC16F877-20I/L (PLCC-44(16.6x16.6)) — * Controlling Parameter | Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-022 Drawing No. C04-071 | B | D1 | E | CH | 15 10 5 15
* Controlling Parameter | Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-022 Drawing No. C04-071 | B | D1 | E | CH | 15 10 5 15
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (PIC16F877-20I/L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC16F877-20I/L (PLCC-44(16.6x16.6)) is a 44-pin standard electronic & interconnect component featuring a 16.60 × 16.60 × 1.15 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 2.0V to 5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.0V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
16.60 × 16.60 × 1.15 mm (A1=0.03 mm)
Package family: LGA (PLCC-44(16.6x16.6))
Pin Count & Lead PitchN / e
44 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol44 auto-grouped pins
OK
IPC-7351B Land Pattern44 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PLCC-44(16.6x16.6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
16.60 × 16.60 mm
Height (A) & Pitch (e)IPC-7351B
A=1.15mm · e=1.27mm
Pad Size (W × L)Level B
0.65 × 2.20 mm
Pins / Total PadsTopology
44P / 44Pad (LGA_ARRAY)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PLCC-44(16.6x16.6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16F877-20I/L (PLCC-44(16.6x16.6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16F877-20I/L (PLCC-44(16.6x16.6))?

Manufactured by MICROCHIP, the PIC16F877-20I/L is housed in a PLCC-44(16.6x16.6) package with 44 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 2 (MCLR/VPP: Multiplexed I/O & Peripheral Pin MCLR/VPP (General)), 3 (RA0/AN0: Multiplexed I/O & Peripheral Pin RA0/AN0 (General)), 4 (RA1/AN1: Multiplexed I/O & Peripheral Pin RA1/AN1 (General)), 5 (RA2/AN2/VREF-: Multiplexed I/O & Peripheral Pin RA2/AN2/VREF- (General)), 6 (RA3/AN3/VREF+: Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16F877-20I/L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F877-20I/L (PLCC-44(16.6x16.6)) has a nominal body envelope of 16.60 × 16.60 mm, pitch e = 1.27 mm, and 44 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F877-20I/L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F877-20I/L (MICROCHIP, PLCC-44(16.6x16.6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (44 pins) & PIC16F877 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1NCNCSignal terminal NC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
2MCLR/VPPDigital_IOSignal terminal MCLR/VPP (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: MCLR/VPP. Supported peripheral buses: General.
3RA0/AN0Digital_IOSignal terminal RA0/AN0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA0/AN0. Supported peripheral buses: General.
4RA1/AN1Digital_IOSignal terminal RA1/AN1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA1/AN1. Supported peripheral buses: General.
5RA2/AN2/VREF-AnalogSignal terminal RA2/AN2/VREF- (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA2/AN2/VREF-. Supported peripheral buses: General.
6RA3/AN3/VREF+AnalogSignal terminal RA3/AN3/VREF+ (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA3/AN3/VREF+. Supported peripheral buses: General.
7RA4/T0CKIDigital_IOSignal terminal RA4/T0CKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA4/T0CKI. Supported peripheral buses: General.
8RA5/AN4/SSDigital_IOSignal terminal RA5/AN4/SS (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA5/AN4/SS. Supported peripheral buses: General.
9RE0/AN5/RDDigital_IOSignal terminal RE0/AN5/RD (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE0/AN5/RD. Supported peripheral buses: General.
10RE1/AN6/WRDigital_IOSignal terminal RE1/AN6/WR (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE1/AN6/WR. Supported peripheral buses: General.
11RE2/AN7/CSDigital_IOSignal terminal RE2/AN7/CS (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE2/AN7/CS. Supported peripheral buses: General.
12VDDPower_InPrimary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
13VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
14OSC1/CLKINDigital_IOSignal terminal OSC1/CLKIN (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC1/CLKIN. Supported peripheral buses: RTC/CLK.
15OSC2/CLKOUTDigital_IOSignal terminal OSC2/CLKOUT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC2/CLKOUT. Supported peripheral buses: RTC/CLK.
16RC0/T1OSO/T1CKIDigital_IOSignal terminal RC0/T1OSO/T1CKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC0/T1OSO/T1CKI. Supported peripheral buses: General.
17NCNCSignal terminal NC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
18STATUSDigital_IOSignal terminal STATUS (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: STATUS. Supported peripheral buses: General.
19OPTION_REGDigital_IOSignal terminal OPTION_REG (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OPTION_REG. Supported peripheral buses: General.
20INTCONDigital_IOSignal terminal INTCON (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: INTCON. Supported peripheral buses: General.
21PIE1Digital_IOSignal terminal PIE1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: PIE1. Supported peripheral buses: General.
22PIR1Digital_IOSignal terminal PIR1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: PIR1. Supported peripheral buses: General.
23PIE2Digital_IOSignal terminal PIE2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: PIE2. Supported peripheral buses: General.
24PIR2Digital_IOSignal terminal PIR2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: PIR2. Supported peripheral buses: General.
25PCONDigital_IOSignal terminal PCON (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: PCON. Supported peripheral buses: General.
26PCLATHDigital_IOSignal terminal PCLATH (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: PCLATH. Supported peripheral buses: General.
27FSRDigital_IOSignal terminal FSR (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: FSR. Supported peripheral buses: General.
28NCNCSignal terminal NC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
29TRISADigital_IOSignal terminal TRISA (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: TRISA. Supported peripheral buses: General.
30RD4/PSP4Digital_IOSignal terminal RD4/PSP4 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD4/PSP4. Supported peripheral buses: General.
31TRISBDigital_IOSignal terminal TRISB (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: TRISB. Supported peripheral buses: General.
32RD6/PSP6Digital_IOSignal terminal RD6/PSP6 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD6/PSP6. Supported peripheral buses: General.
33TRISCDigital_IOSignal terminal TRISC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: TRISC. Supported peripheral buses: General.
34VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
35TRISDDigital_IOSignal terminal TRISD (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: TRISD. Supported peripheral buses: General.
36PORTEDigital_IOSignal terminal PORTE (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: PORTE. Supported peripheral buses: General.
37TRISEDigital_IOSignal terminal TRISE (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: TRISE. Supported peripheral buses: General.
38RB2Digital_IOSignal terminal RB2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB2. Supported peripheral buses: General.
39RB3/PGMDigital_IOSignal terminal RB3/PGM (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB3/PGM. Supported peripheral buses: General.
40NCNCSignal terminal NC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
41EECON2Digital_IOSignal terminal EECON2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: EECON2. Supported peripheral buses: General.
42EECON1Digital_IOSignal terminal EECON1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: EECON1. Supported peripheral buses: General.
43RB6/PGCDigital_IOSignal terminal RB6/PGC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB6/PGC. Supported peripheral buses: General.
44RB7/PGDDigital_IOSignal terminal RB7/PGD (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB7/PGD. Supported peripheral buses: General.
ExplorePartsPackagesMFRsUpload