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ESP-WROOM-02-N2 (SMD-18P) — Symbol, Footprint IPC-7351B & 3D STEP Model

ESP-WROOM-02-N2

ESPRESSIFID: C81770SMD-18P · 19 Pins · Pitch 1.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ESP-WROOM-02-N2 (SMD-18P)13V32EN3IO144IO125IO136IO157IO28IO09GND10IO419EP18GND17IO1616TOUT15RST14IO513GND12TXD11RXDGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
ANTENNA KEEPOUT (6.3mm)12345678910111213141516171819E=18.00mm · Pitch e=1.50mmD=20.00mm-15-13-11-9-7-5-3-11357911131515131197531-1-3-5-7-9-11-13-15mm
3. 3D CAD MODEL
Package Body: 18.00mm × 20.00mm · Pitch: 1.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (19/19)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
13V3PowerPower Supply Input (3V3 — 2.7 V ~ 3.6 V)
2ENISystem Enable & Hardware Reset (EN)
3IO14I/OMultiplexed I/O & Peripheral Pin IO14 (General)
4IO12I/OMultiplexed I/O & Peripheral Pin IO12 (General)
5IO13I/OMultiplexed I/O & Peripheral Pin IO13 (General)
6IO15I/OMultiplexed I/O & Peripheral Pin IO15 (General)
7IO2I/OMultiplexed I/O & Peripheral Pin IO2 (General)
8IO0I/OMultiplexed I/O & Peripheral Pin IO0 (General)
9GNDGNDGround Reference Pin (GND)
10IO4I/OMultiplexed I/O & Peripheral Pin IO4 (General)
11RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
12TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
13GNDGNDGround Reference Pin (GND)
14IO5I/OMultiplexed I/O & Peripheral Pin IO5 (General)
15RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
16TOUTI/OMultiplexed I/O & Peripheral Pin TOUT (General)
17IO16I/OMultiplexed I/O & Peripheral Pin IO16 (General)
18GNDGNDGround Reference Pin (GND)
19EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 3V3
Power
Power Supply Input (3V3 — 2.7 V ~ 3.6 V)
Design note: Primary positive power supply input (3V3) operating in the 2.7 V ~ 3.6 V domain (Max rating: 3.6V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ESP-WROOM-02-N2 (ESPRESSIF · SMD-18P)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ESP-WROOM-02-N2 (SMD-18P) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ESP-WROOM-02-N2 (SMD-18P) - 2. Standard Pinout (Top View)
True package pinout (19 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ESP-WROOM-02-N2 (SMD-18P) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ESP-WROOM-02-N2 (SMD-18P) - 4. Package Dimensions (D×E×A)
SMD-18P · 18.00×20.00mm · Pitch 1.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
ESP-WROOM-02-N2 (SMD-18P) - 5. Recommended Land Pattern
IPC-7351B Footprint (19 Pads)Expand ›
6. Application SchematicSCHEMATIC
ESP-WROOM-02-N2 (SMD-18P) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for ESP-WROOM
P8 · p08_fig01EXACT PACKAGE
ESP-WROOM-02-N2 (SMD-18P) — 图 2-1. ESP-WROOM-02 模组管脚分布（俯视图）
图 2-1. ESP-WROOM-02 模组管脚分布（俯视图）
P16 · p16_fig01EXACT PACKAGE
ESP-WROOM-02-N2 (SMD-18P) — 图 5-1. ESP-WROOM-02 模组原理图
图 5-1. ESP-WROOM-02 模组原理图
P17 · p17_fig01EXACT PACKAGE
ESP-WROOM-02-N2 (SMD-18P) — 图 5-2. ESP-WROOM-02 模组外围设计原理图
图 5-2. ESP-WROOM-02 模组外围设计原理图
P18 · p18_fig01EXACT PACKAGE
ESP-WROOM-02-N2 (SMD-18P) — 图 6-1. ESP-WROOM-02 模组尺⼨图
图 6-1. ESP-WROOM-02 模组尺⼨图
P19 · p19_fig01EXACT PACKAGE
ESP-WROOM-02-N2 (SMD-18P) — 图 7-1. ESP-WROOM-02 PCB 封装图形
图 7-1. ESP-WROOM-02 PCB 封装图形
P16 · p16_fig01P16
ESP-WROOM-02-N2 (SMD-18P) — Datasheet Page 16 (p16_fig01)
Datasheet Page 16 (p16_fig01)
P18 · p18_fig01P18
ESP-WROOM-02-N2 (SMD-18P) — Datasheet Page 18 (p18_fig01)
Datasheet Page 18 (p18_fig01)
P19 · p19_fig01P19
ESP-WROOM-02-N2 (SMD-18P) — Datasheet Page 19 (p19_fig01)
Datasheet Page 19 (p19_fig01)

Technical Specifications & Part Details (ESP-WROOM-02-N2)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:ESP-WROOM-02-N2 (SMD-18P) is a 18-pin wireless wi-fi / bluetooth le soc module featuring a 20.00 × 18.00 × 3.10 mm mechanical envelope (lead pitch e = 1.49 mm). Rated for 2.7 V ~ 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Wi-Fi, UART interfaces.
Operating Supply VoltageV_CC / V_DD
2.7 V ~ 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2484 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
20.00 × 18.00 × 3.10 mm (A1=0.00 mm)
Package family: CASTELLATED_MODULE (SMD-18P)
Pin Count & Lead PitchN / e
18 Pins | Pitch e = 1.49 mm (58.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (IO0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol19 auto-grouped pins
OK
IPC-7351B Land Pattern19 pads · Pitch 1.50mm
OK
IPC-7525 60% Solder PasteEPAD 4.40×4.40mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SMD-18P)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
20.00 × 18.00 mm
Height (A) & Pitch (e)IPC-7351B
A=3.10mm · e=1.50mm
Pad Size (W × L)Level B
0.90 × 1.49 mm
Pins / Total PadsTopology
19P / 19Pad (CASTELLATED_MODULE)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SMD-18P
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ESP-WROOM-02-N2 (SMD-18P)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ESP-WROOM-02-N2 (SMD-18P)?

Manufactured by ESPRESSIF, the ESP-WROOM-02-N2 is housed in a SMD-18P package with 19 pins and a 1.50 mm lead pitch, supporting a VCC supply range of 2.7 V ~ 3.6 V. Key pins include: 1 (3V3: Power Supply Input (3V3 — 2.7 V ~ 3.6 V)), 2 (EN: System Enable & Hardware Reset (EN)), 3 (IO14: Multiplexed I/O & Peripheral Pin IO14 (General)), 4 (IO12: Multiplexed I/O & Peripheral Pin IO12 (General)), 5 (IO13: Multiplexed I/O & Peripheral Pin IO13 (General)), 6 (IO15: Multiplexed I/O & Peripheral Pin IO15 (General)).

What are the IPC-7351B PCB Footprint dimensions for ESP-WROOM-02-N2?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP-WROOM-02-N2 (SMD-18P) has a nominal body envelope of 18.00 × 20.00 mm, pitch e = 1.50 mm, and 19 copper pads plus a central exposed thermal pad (EPAD) of 4.40 × 4.40 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP-WROOM-02-N2?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP-WROOM-02-N2 (ESPRESSIF, SMD-18P) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (19 pins) & ESP-WROOM Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
13V3Power_InPrimary positive power supply input (3V3) operating in the 2.7 V ~ 3.6 V domain (Max rating: 3.6V).
2ENDigital_IOChip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset.
3IO14Digital_IOSignal terminal IO14 (I/O, 2.7 V ~ 3.6 V domain). Multiplexed alternate functions: IO14. Supported peripheral buses: General.
4IO12Digital_IOSignal terminal IO12 (I/O, 2.7 V ~ 3.6 V domain). Multiplexed alternate functions: IO12. Supported peripheral buses: General.
5IO13Digital_IOSignal terminal IO13 (I/O, 2.7 V ~ 3.6 V domain). Multiplexed alternate functions: IO13. Supported peripheral buses: General.
6IO15Digital_IOSignal terminal IO15 (I/O, 2.7 V ~ 3.6 V domain). Multiplexed alternate functions: IO15. Supported peripheral buses: General.
7IO2Digital_IOSignal terminal IO2 (I/O, 2.7 V ~ 3.6 V domain). Multiplexed alternate functions: IO2. Supported peripheral buses: General.
8IO0Digital_IOSignal terminal IO0 (I/O, 2.7 V ~ 3.6 V domain). Multiplexed alternate functions: IO0. Supported peripheral buses: General.
9GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
10IO4Digital_IOSignal terminal IO4 (I/O, 2.7 V ~ 3.6 V domain). Multiplexed alternate functions: IO4. Supported peripheral buses: General.
11RXDDigital_IOSignal terminal RXD (I/O, 2.7 V ~ 3.6 V domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
12TXDDigital_IOSignal terminal TXD (I/O, 2.7 V ~ 3.6 V domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
13GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
14IO5Digital_IOSignal terminal IO5 (I/O, 2.7 V ~ 3.6 V domain). Multiplexed alternate functions: IO5. Supported peripheral buses: General.
15RSTDigital_IOSignal terminal RST (I/O, 2.7 V ~ 3.6 V domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
16TOUTDigital_IOSignal terminal TOUT (I/O, 2.7 V ~ 3.6 V domain). Multiplexed alternate functions: TOUT. Supported peripheral buses: General.
17IO16Digital_IOSignal terminal IO16 (I/O, 2.7 V ~ 3.6 V domain). Multiplexed alternate functions: IO16. Supported peripheral buses: General.
18GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
19EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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