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CH32V303CBT6 (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32V303CBT6

WCHID: C7494374LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32V303CBT6 (LQFP-48(7x7))1OSC_IN2PC13/TAMPER_3PC14/OSC32IN4PC05PC16PC27PC38VSSA9VDDA10PA0 WKUP -11PA112PA213PA314PA415PA5（15）16PA617PA718PC419PC520PB021PB122PB1123PB1024PB1148VDD_IO3_47VSS_346PB945PB844PB743PB642PB541PB440PB339PA1538PA1437PA1336PA1235PA1134PA1033PA932PA831PC630PB1529PB1428PB1327PB1226VSS_125VDD_IO1_Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.835.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
2PC13/TAMPER_RTCI/OMultiplexed I/O & Peripheral Pin PC13/TAMPER_RTC (RTC/CLK)
3PC14/OSC32INI/OMultiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK)
4PC0I/OMultiplexed I/O & Peripheral Pin PC0 (PWM)
5PC1I/OMultiplexed I/O & Peripheral Pin PC1 (UART, ADC, PWM)
6PC2I/OMultiplexed I/O & Peripheral Pin PC2 (UART, PWM)
7PC3I/OMultiplexed I/O & Peripheral Pin PC3 (UART)
8VSSAGNDGround Reference Pin (VSSA)
9VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
10PA0 WKUP -I/OMultiplexed I/O & Peripheral Pin PA0 WKUP - (General)
11PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
12PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
13PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
14PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC, PWM)
15PA5（15）I/OMultiplexed I/O & Peripheral Pin PA5（15） (DAC)
16PA6I/OMultiplexed I/O & Peripheral Pin PA6 (ADC, PWM)
17PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
18PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, PWM)
19PC5I/OMultiplexed I/O & Peripheral Pin PC5 (ADC)
20PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
21PB1I/OMultiplexed I/O & Peripheral Pin PB1 (PWM)
22PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
23PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, I2C)
24PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C)
25VDD_IO1_PowerPower Supply Input (VDD_IO1_ — 3.3V / 5.0V Standard Logic)
26VSS_1GNDGround Reference Pin (VSS_1)
27PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C, CAN)
28PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
29PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, PWM)
30PB15I/OMultiplexed I/O & Peripheral Pin PB15 (UART, SPI)
31PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
32PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, PWM, RTC/CLK)
33PA9I/OMultiplexed I/O & Peripheral Pin PA9 (PWM)
34PA10I/OMultiplexed I/O & Peripheral Pin PA10 (PWM)
35PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, PWM, CAN)
36PA12I/OMultiplexed I/O & Peripheral Pin PA12 (CAN)
37PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
38PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
39PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SPI)
40PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI)
41PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI)
42PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
43PB6I/OMultiplexed I/O & Peripheral Pin PB6 (USB, I2C, PWM)
44PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
45PB8I/OMultiplexed I/O & Peripheral Pin PB8 (PWM)
46PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
47VSS_3GNDGround Reference Pin (VSS_3)
48VDD_IO3_PowerPower Supply Input (VDD_IO3_ — 3.3V / 5.0V Standard Logic)
PIN 1 OSC_IN
I/O
Multiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
Design note: PD0(4)
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32V303CBT6 (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32V303CBT6 (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32V303CBT6 (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32V303CBT6 (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32V303CBT6 (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32V303CBT6 (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32V303CBT6 (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for CH32V208 / CH32V305 / CH32V307
P95 · p95_fig02EXACT PACKAGE
CH32V303CBT6 (LQFP-48(7x7)) — 5.3 LQFP48 Package
5.3 LQFP48 Package
P1 · p01_fig01278×168px
CH32V303CBT6 (LQFP-48(7x7)) — Overview
Overview
P3 · p03_fig011812×1679px
CH32V303CBT6 (LQFP-48(7x7)) — V3.8 1
V3.8 1
P3 · p03_fig01P3
CH32V303CBT6 (LQFP-48(7x7)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P25 · p25_fig011472×899px
CH32V303CBT6 (LQFP-48(7x7)) — 3.1.1 Interconnectivity Device V307
3.1.1 Interconnectivity Device V307
P88 · p88_fig011852×541px
CH32V303CBT6 (LQFP-48(7x7)) — CH32V303/305/307/317 Datasheet https://wch-ic.com
CH32V303/305/307/317 Datasheet https://wch-ic.com
P88 · p88_fig021852×1111px
CH32V303CBT6 (LQFP-48(7x7)) — The above formula is used to determine the maximum external impedance so that the error can be less than 1/4 LSB. Where N=12 (representing 12-bit resolution). | Table 4-43 Maximum RAIN when fADC = 14MHz | TS(cycle) tS (us) Maximum RAIN(kΩ)
The above formula is used to determine the maximum external impedance so that the error can be less than 1/4 LSB. Where N=12 (representing 12-bit resolution). | Table 4-43 Maximum RAIN when fADC = 14MHz | TS(cycle) tS (us) Maximum RAIN(kΩ)
P88 · p88_fig01P88
CH32V303CBT6 (LQFP-48(7x7)) — Datasheet Page 88 (p88_fig01)
Datasheet Page 88 (p88_fig01)
P95 · p95_fig011344×1020px
CH32V303CBT6 (LQFP-48(7x7)) — 5.2 QFN28 Package
5.2 QFN28 Package
P95 · p95_fig01P95
CH32V303CBT6 (LQFP-48(7x7)) — Datasheet Page 95 (p95_fig01)
Datasheet Page 95 (p95_fig01)
P98 · p98_fig011564×2234px
CH32V303CBT6 (LQFP-48(7x7)) — G = 28 pins K = 32 pins T = 36 pins C = 48 pins R = 64 pins
G = 28 pins K = 32 pins T = 36 pins C = 48 pins R = 64 pins
P97 · p97_fig01All Packages in PDF
CH32V303CBT6 (LQFP-48(7x7)) — 5.6 LQFP100 Package
5.6 LQFP100 Package

Technical Specifications & Part Details (CH32V303CBT6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:CH32V303CBT6 (LQFP-48(7x7)) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, CAN, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
144MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, CAN, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32V303CBT6 (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32V303CBT6 (LQFP-48(7x7))?

Manufactured by WCH, the CH32V303CBT6 is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (OSC_IN: Multiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)), 2 (PC13/TAMPER_RTC: Multiplexed I/O & Peripheral Pin PC13/TAMPER_RTC (RTC/CLK)), 3 (PC14/OSC32IN: Multiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK)), 4 (PC0: Multiplexed I/O & Peripheral Pin PC0 (PWM)), 5 (PC1: Multiplexed I/O & Peripheral Pin PC1 (UART, ADC, PWM)), 6 (PC2: Multiplexed I/O & Peripheral Pin PC2 (UART, PWM)).

What are the IPC-7351B PCB Footprint dimensions for CH32V303CBT6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32V303CBT6 (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32V303CBT6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32V303CBT6 (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH32V208 / CH32V305 / CH32V307 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
2PC13/TAMPER_RTCDigital_IOSignal terminal PC13/TAMPER_RTC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13/TAMPER_RTC. Supported peripheral buses: RTC/CLK.
3PC14/OSC32INDigital_IOSignal terminal PC14/OSC32IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14/OSC32IN. Supported peripheral buses: RTC/CLK.
4PC0Digital_IOSignal terminal PC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0. Supported peripheral buses: PWM.
5PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: UART, ADC, PWM.
6PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2. Supported peripheral buses: UART, PWM.
7PC3Digital_IOSignal terminal PC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3. Supported peripheral buses: UART.
8VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
9VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
10PA0 WKUP -Digital_IOSignal terminal PA0 WKUP - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0 WKUP -. Supported peripheral buses: General.
11PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
12PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
13PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
14PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, DAC, PWM.
15PA5（15）Digital_IOSignal terminal PA5（15） (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5（15）. Supported peripheral buses: DAC.
16PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: ADC, PWM.
17PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
18PC4Digital_IOSignal terminal PC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4. Supported peripheral buses: UART, PWM.
19PC5Digital_IOSignal terminal PC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC.
20PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
21PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: PWM.
22PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
23PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: UART, I2C.
24PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: UART, I2C.
25VDD_IO1_Power_InPrimary positive power supply input (VDD_IO1_) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
26VSS_1GND0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks.
27PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_NSS, I2C2_SMBA. Supported peripheral buses: UART, SPI, I2C, CAN.
28PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
29PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: UART, PWM.
30PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: UART, SPI.
31PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
32PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, PWM, RTC/CLK.
33PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: PWM.
34PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: PWM.
35PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: UART, PWM, CAN.
36PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: CAN.
37PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
38PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
39PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: SPI.
40PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: SPI.
41PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: SPI.
42PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
43PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: USB, I2C, PWM.
44PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
45PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: PWM.
46PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
47VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
48VDD_IO3_Power_InPrimary positive power supply input (VDD_IO3_) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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