ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH397A (QFN-24(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH397A

WCHID: C7465328QFN-24(4x4) · 25 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH397A (QFN-24(4x4))1AVDD332MDITP3MDITN4MDIRP5MDIRN6GND7UDM8UDP9DVDDK10AVDD3311V512NC13VDDIO25GND24GND23AVDDK22XO21XI20SDIO19NC18VDDIO17LED116NC15LED014GPIO6Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.222.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425E=4.00mm · Pitch e=0.50mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (25/25)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1AVDD33PowerPower Supply Input (AVDD33 — 3.3V / 5.0V Standard Logic)
2MDITPI/OMultiplexed I/O & Peripheral Pin MDITP (General)
3MDITNI/OMultiplexed I/O & Peripheral Pin MDITN (General)
4MDIRPI/OMultiplexed I/O & Peripheral Pin MDIRP (General)
5MDIRNI/OMultiplexed I/O & Peripheral Pin MDIRN (General)
6GNDGNDGround Reference Pin (GND)
7UDMI/OMultiplexed I/O & Peripheral Pin UDM (General)
8UDPI/OMultiplexed I/O & Peripheral Pin UDP (General)
9DVDDKPowerPower Supply Input (DVDDK — 3.3V / 5.0V Standard Logic)
10AVDD33PowerPower Supply Input (AVDD33 — 3.3V / 5.0V Standard Logic)
11V5I/OMultiplexed I/O & Peripheral Pin V5 (General)
12NCI/OMultiplexed I/O & Peripheral Pin NC (General)
13VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
14GPIO6I/OMultiplexed I/O & Peripheral Pin GPIO6 (General)
15LED0I/OMultiplexed I/O & Peripheral Pin LED0 (General)
16NCI/OMultiplexed I/O & Peripheral Pin NC (General)
17LED1I/OMultiplexed I/O & Peripheral Pin LED1 (General)
18VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
19NCI/OMultiplexed I/O & Peripheral Pin NC (General)
20SDIOI/OMultiplexed I/O & Peripheral Pin SDIO (General)
21XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
22XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
23AVDDKPowerPower Supply Input (AVDDK — 3.3V / 5.0V Standard Logic)
24GNDGNDGround Reference Pin (GND)
25GNDGNDGround Reference Pin (GND)
PIN 1 AVDD33
Power
Power Supply Input (AVDD33 — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (AVDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH397A (WCH · QFN-24(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH397A (QFN-24(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH397A (QFN-24(4x4)) - 2. Standard Pinout (Top View)
True package pinout (25 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH397A (QFN-24(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH397A (QFN-24(4x4)) - 4. Package Dimensions (D×E×A)
QFN-24(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH397A (QFN-24(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (25 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH397A (QFN-24(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for CH397
P9 · p09_fig01EXACT PACKAGE
CH397A (QFN-24(4x4)) — 5.2 QFN32_4x4
5.2 QFN32_4x4
P1 · p01_fig01309×165px
CH397A (QFN-24(4x4)) — 概述
概述
P2 · p02_fig011620×973px
CH397A (QFN-24(4x4)) — 图1-1 CH397 引脚分布
图1-1 CH397 引脚分布
P2 · p02_fig01P2
CH397A (QFN-24(4x4)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P9 · p09_fig021341×1018px
CH397A (QFN-24(4x4)) — 5.2 QFN32_4x4
5.2 QFN32_4x4
P10 · p10_fig011569×1697px
CH397A (QFN-24(4x4)) — R1/R2/LED0/LED1 是可选的LED 指示。对于批号倒数第6 位为8 的CH397 芯片，GPIO6 引脚默认
R1/R2/LED0/LED1 是可选的LED 指示。对于批号倒数第6 位为8 的CH397 芯片，GPIO6 引脚默认
P10 · p10_fig01P10
CH397A (QFN-24(4x4)) — Datasheet Page 10 (p10_fig01)
Datasheet Page 10 (p10_fig01)

Technical Specifications & Part Details (CH397A)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH397A (QFN-24(4x4)) is a 24-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, SDIO, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-24(4x4))
Pin Count & Lead PitchN / e
24 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, SDIO, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol25 auto-grouped pins
OK
IPC-7351B Land Pattern25 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.80×2.80mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-24(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
25P / 25Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-24(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH397A (QFN-24(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH397A (QFN-24(4x4))?

Manufactured by WCH, the CH397A is housed in a QFN-24(4x4) package with 25 pins and a 0.50 mm lead pitch. Key pins include: 1 (AVDD33: Power Supply Input (AVDD33 — 3.3V / 5.0V Standard Logic)), 2 (MDITP: Multiplexed I/O & Peripheral Pin MDITP (General)), 3 (MDITN: Multiplexed I/O & Peripheral Pin MDITN (General)), 4 (MDIRP: Multiplexed I/O & Peripheral Pin MDIRP (General)), 5 (MDIRN: Multiplexed I/O & Peripheral Pin MDIRN (General)), 6 (GND: Ground Reference Pin (GND)).

What are the IPC-7351B PCB Footprint dimensions for CH397A?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH397A (QFN-24(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 25 copper pads plus a central exposed thermal pad (EPAD) of 2.80 × 2.80 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH397A?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH397A (WCH, QFN-24(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (25 pins) & CH397 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1AVDD33Power_InPrimary positive power supply input (AVDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2MDITPDigital_IOSignal terminal MDITP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITP. Supported peripheral buses: General.
3MDITNDigital_IOSignal terminal MDITN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITN. Supported peripheral buses: General.
4MDIRPDigital_IOSignal terminal MDIRP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRP. Supported peripheral buses: General.
5MDIRNDigital_IOSignal terminal MDIRN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRN. Supported peripheral buses: General.
6GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
7UDMDigital_IOSignal terminal UDM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UDM. Supported peripheral buses: General.
8UDPDigital_IOSignal terminal UDP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UDP. Supported peripheral buses: General.
9DVDDKPower_InPrimary positive power supply input (DVDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
10AVDD33Power_InPrimary positive power supply input (AVDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
11V5Digital_IOSignal terminal V5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V5. Supported peripheral buses: General.
12NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
13VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14GPIO6Digital_IOSignal terminal GPIO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO6. Supported peripheral buses: General.
15LED0Digital_IOSignal terminal LED0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED0. Supported peripheral buses: General.
16NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
17LED1Digital_IOSignal terminal LED1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED1. Supported peripheral buses: General.
18VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
19NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
20SDIODigital_IOSignal terminal SDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDIO. Supported peripheral buses: General.
21XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
22XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
23AVDDKPower_InPrimary positive power supply input (AVDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
24GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
25GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
ExplorePartsPackagesMFRsUpload