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ATWINC3400-MR210UA142 (SMD-36P) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATWINC3400-MR210UA142

MICROCHIPID: C7218385SMD-36P · 37 Pins · Pitch 1.20mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATWINC3400-MR210UA142 (SMD-36P)1GND2SPI_CFG3NC4NC5NC6NC7RESETN8BT_TXD9BT_RXD10I2C_SDAS_11I2C_SCLS_12VDDIO13GND14GPIO315GPIO416UART_TXD17UART_RXD18VBAT19CHIP_EN37PADDLEVSS36GND35I2C_SDAM_34I2C_SCLM_33IRQN32GPIO2031GPIO1930GPIO1829GPIO1728GND27GPIO726SPI_MOSI25SPI_SSN24SPI_MISO23SPI_SCK22GPIO821GND20RTC_CLKGrid Pitch = 2.54mm (IEEE-315)-20.3-15.2-10.2-5.105.110.215.220.330.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5mm
2. 2D FOOTPRINT
ANTENNA KEEPOUT (5.3mm)12345678910111213141516171819202122232425262728293031323334353637E=14.73mm · Pitch e=1.20mmD=22.43mm-14-12-10-8-6-4-2024681012141715131197531-1-3-5-7-9-11-13-15-17mm
3. 3D CAD MODEL
Package Body: 14.73mm × 22.43mm · Pitch: 1.20mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (37/37)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GNDGNDGround Reference Pin (GND)
2SPI_CFGI/OMultiplexed I/O & Peripheral Pin SPI_CFG (SPI)
3NCI/OMultiplexed I/O & Peripheral Pin NC (General)
4NCI/OMultiplexed I/O & Peripheral Pin NC (General)
5NCI/OMultiplexed I/O & Peripheral Pin NC (General)
6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
7RESETNISystem Enable & Hardware Reset (RESETN)
8BT_TXDI/OMultiplexed I/O & Peripheral Pin BT_TXD (UART, SPI)
9BT_RXDI/OMultiplexed I/O & Peripheral Pin BT_RXD (UART, SPI)
10I2C_SDAS_I/OMultiplexed I/O & Peripheral Pin I2C_SDAS_ (I2C)
11I2C_SCLS_I/OMultiplexed I/O & Peripheral Pin I2C_SCLS_ (I2C)
12VDDIOPowerPower Supply Input (VDDIO — 2.7V to 3.6V)
13GNDGNDGround Reference Pin (GND)
14GPIO3I/OMultiplexed I/O & Peripheral Pin GPIO3 (General)
15GPIO4I/OMultiplexed I/O & Peripheral Pin GPIO4 (General)
16UART_TXDI/OMultiplexed I/O & Peripheral Pin UART_TXD (UART)
17UART_RXDI/OMultiplexed I/O & Peripheral Pin UART_RXD (UART)
18VBATPowerPower Supply Input (VBAT — 2.7V to 3.6V)
19CHIP_ENI/OMultiplexed I/O & Peripheral Pin CHIP_EN (General)
20RTC_CLKI/OMultiplexed I/O & Peripheral Pin RTC_CLK (RTC/CLK)
21GNDGNDGround Reference Pin (GND)
22GPIO8I/OMultiplexed I/O & Peripheral Pin GPIO8 (General)
23SPI_SCKI/OMultiplexed I/O & Peripheral Pin SPI_SCK (SPI)
24SPI_MISOI/OMultiplexed I/O & Peripheral Pin SPI_MISO (SPI)
25SPI_SSNI/OMultiplexed I/O & Peripheral Pin SPI_SSN (SPI)
26SPI_MOSII/OMultiplexed I/O & Peripheral Pin SPI_MOSI (SPI)
27GPIO7I/OMultiplexed I/O & Peripheral Pin GPIO7 (General)
28GNDGNDGround Reference Pin (GND)
29GPIO17I/OMultiplexed I/O & Peripheral Pin GPIO17 (General)
30GPIO18I/OMultiplexed I/O & Peripheral Pin GPIO18 (General)
31GPIO19I/OMultiplexed I/O & Peripheral Pin GPIO19 (General)
32GPIO20I/OMultiplexed I/O & Peripheral Pin GPIO20 (General)
33IRQNI/OMultiplexed I/O & Peripheral Pin IRQN (General)
34I2C_SCLM_I/OMultiplexed I/O & Peripheral Pin I2C_SCLM_ (I2C)
35I2C_SDAM_I/OMultiplexed I/O & Peripheral Pin I2C_SDAM_ (I2C)
36GNDGNDGround Reference Pin (GND)
37PADDLEVSSGNDGround Reference Pin (PADDLEVSS)
PIN 1 GND
GND
Ground Reference Pin (GND)
Design note: Groundpin
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ATWINC3400-MR210UA142 (MICROCHIP · SMD-36P)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ATWINC3400-MR210UA142 (SMD-36P) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATWINC3400-MR210UA142 (SMD-36P) - 2. Standard Pinout (Top View)
True package pinout (37 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATWINC3400-MR210UA142 (SMD-36P) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATWINC3400-MR210UA142 (SMD-36P) - 4. Package Dimensions (D×E×A)
SMD-36P · 14.73×22.43mm · Pitch 1.20mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATWINC3400-MR210UA142 (SMD-36P) - 5. Recommended Land Pattern
IPC-7351B Footprint (37 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATWINC3400-MR210UA142 (SMD-36P) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for ATWINC3400
P1 · p01_fig01456×280px
ATWINC3400-MR210UA142 (SMD-36P) — IEEE® 802.11 b/g/n Network Controller with Integrated
IEEE® 802.11 b/g/n Network Controller with Integrated
P7 · p07_fig011257×1356px
ATWINC3400-MR210UA142 (SMD-36P) — The following table provides the ATWINC3400-MR210xA module pin description.
The following table provides the ATWINC3400-MR210xA module pin description.
P30 · p30_fig011336×379px
ATWINC3400-MR210UA142 (SMD-36P) — Figure 10-4. Example of UART RX of TX Packet
Figure 10-4. Example of UART RX of TX Packet
P33 · p33_fig011669×1083px
ATWINC3400-MR210UA142 (SMD-36P) — Figure 11-1. ATWINC3400-MR210xA Reference Schematic
Figure 11-1. ATWINC3400-MR210xA Reference Schematic
P33 · p33_fig01P33
ATWINC3400-MR210UA142 (SMD-36P) — Datasheet Page 33 (p33_fig01)
Datasheet Page 33 (p33_fig01)
P35 · p35_fig011648×1809px
ATWINC3400-MR210UA142 (SMD-36P) — 12. Module Outline Drawings
12. Module Outline Drawings
P35 · p35_fig01P35
ATWINC3400-MR210UA142 (SMD-36P) — Datasheet Page 35 (p35_fig01)
Datasheet Page 35 (p35_fig01)
P36 · p36_fig011012×648px
ATWINC3400-MR210UA142 (SMD-36P) — Figure 12-2. ATWINC3400-MR210CA Module Package Drawings - 3D View and Recommended Land Pattern
Figure 12-2. ATWINC3400-MR210CA Module Package Drawings - 3D View and Recommended Land Pattern
P36 · p36_fig021431×1176px
ATWINC3400-MR210UA142 (SMD-36P) — RECOMMENDED LAND PATTERN | 1.985 | 12.045 | 25 36 | 24 | 14 | 13 1 | SILK SCREEN | 22.428 | EDGE OF PC BOARD | 4.400 | 4.400 | 13.244 | 6.128 | 5.118 | 5.214 | 14.732 | 1.204 PITCH | 0.813 | 1.880 | RECOMMENDED LAND PATTERN | 1.985 | 12.045
RECOMMENDED LAND PATTERN | 1.985 | 12.045 | 25 36 | 24 | 14 | 13 1 | SILK SCREEN | 22.428 | EDGE OF PC BOARD | 4.400 | 4.400 | 13.244 | 6.128 | 5.118 | 5.214 | 14.732 | 1.204 PITCH | 0.813 | 1.880 | RECOMMENDED LAND PATTERN | 1.985 | 12.045
P38 · p38_fig011001×641px
ATWINC3400-MR210UA142 (SMD-36P) — Figure 12-4. ATWINC3400-MR210UA Module Package Drawings - 3D View and Recommended Land Pattern
Figure 12-4. ATWINC3400-MR210UA Module Package Drawings - 3D View and Recommended Land Pattern
P38 · p38_fig021593×1229px
ATWINC3400-MR210UA142 (SMD-36P) — RECOMMENDED LAND PATTERN | 1.985 | 12.045 | 25 36 | 24 | 14 | 13 1 | SILK SCREEN | 22.428 | EDGE OF PC BOARD | 4.400 | 4.400 | 13.244 | 6.128 | 5.118 | 5.214 | 14.732 | 1.204 PITCH | 0.813 | 1.880 | Notes:
RECOMMENDED LAND PATTERN | 1.985 | 12.045 | 25 36 | 24 | 14 | 13 1 | SILK SCREEN | 22.428 | EDGE OF PC BOARD | 4.400 | 4.400 | 13.244 | 6.128 | 5.118 | 5.214 | 14.732 | 1.204 PITCH | 0.813 | 1.880 | Notes:
P38 · p38_fig02P38
ATWINC3400-MR210UA142 (SMD-36P) — Datasheet Page 38 (p38_fig02)
Datasheet Page 38 (p38_fig02)

Technical Specifications & Part Details (ATWINC3400-MR210UA142)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:ATWINC3400-MR210UA142 (SMD-36P) is a 36-pin wireless wi-fi / bluetooth le soc module featuring a 22.43 × 14.73 × 2.40 mm mechanical envelope (lead pitch e = 1.20 mm). Rated for 2.7V to 3.6V supply operation across -40°C to +85°C with integrated Wi-Fi, Bluetooth / BLE, UART, SPI, I2C, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32.768 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
22.43 × 14.73 × 2.40 mm (A1=0.00 mm)
Package family: CASTELLATED_MODULE (SMD-36P)
Pin Count & Lead PitchN / e
36 Pins | Pitch e = 1.20 mm (47.4 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, Bluetooth / BLE, UART, SPI, I2C, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol37 auto-grouped pins
OK
IPC-7351B Land Pattern37 pads · Pitch 1.20mm
OK
IPC-7525 60% Solder PasteEPAD 4.40×4.40mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SMD-36P)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
22.43 × 14.73 mm
Height (A) & Pitch (e)IPC-7351B
A=2.40mm · e=1.20mm
Pad Size (W × L)Level B
0.81 × 1.88 mm
Pins / Total PadsTopology
37P / 37Pad (CASTELLATED_MODULE)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SMD-36P
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATWINC3400-MR210UA142 (SMD-36P)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATWINC3400-MR210UA142 (SMD-36P)?

Manufactured by MICROCHIP, the ATWINC3400-MR210UA142 is housed in a SMD-36P package with 37 pins and a 1.20 mm lead pitch, supporting a VCC supply range of 2.7V to 3.6V. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (SPI_CFG: Multiplexed I/O & Peripheral Pin SPI_CFG (SPI)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 5 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).

What are the IPC-7351B PCB Footprint dimensions for ATWINC3400-MR210UA142?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATWINC3400-MR210UA142 (SMD-36P) has a nominal body envelope of 14.73 × 22.43 mm, pitch e = 1.20 mm, and 37 copper pads plus a central exposed thermal pad (EPAD) of 4.40 × 4.40 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATWINC3400-MR210UA142?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATWINC3400-MR210UA142 (MICROCHIP, SMD-36P) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (37 pins) & ATWINC3400 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
2SPI_CFGDigital_IOSignal terminal SPI_CFG (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPI_CFG. Supported peripheral buses: SPI.
3NCNCSignal terminal NC (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
4NCNCSignal terminal NC (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
5NCNCSignal terminal NC (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
6NCNCSignal terminal NC (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
7RESETNDigital_IOActive-low hardware reset terminal (RESETN): pulling this pin Low resets the processor core and peripherals.
8BT_TXDDigital_IOSignal terminal BT_TXD (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPI. Supported peripheral buses: UART, SPI.
9BT_RXDDigital_IOSignal terminal BT_RXD (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPIISTHEDATAANDCONTROLINTERFACEWITHTHE. Supported peripheral buses: UART, SPI.
10I2C_SDAS_Digital_IOSignal terminal I2C_SDAS_ (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: I2C_SDAS_. Supported peripheral buses: I2C.
11I2C_SCLS_Digital_IOSignal terminal I2C_SCLS_ (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: I2C_SCLS_. Supported peripheral buses: I2C.
12VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 2.7V to 3.6V domain (Max rating: 3.6V).
13GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
14GPIO3Digital_IOSignal terminal GPIO3 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General.
15GPIO4Digital_IOSignal terminal GPIO4 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO4. Supported peripheral buses: General.
16UART_TXDDigital_IOSignal terminal UART_TXD (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: UART_TXD. Supported peripheral buses: UART.
17UART_RXDDigital_IOSignal terminal UART_RXD (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: UART_RXD. Supported peripheral buses: UART.
18VBATPower_InPrimary positive power supply input (VBAT) operating in the 2.7V to 3.6V domain (Max rating: 3.6V).
19CHIP_ENDigital_IOSignal terminal CHIP_EN (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: CHIP_EN. Supported peripheral buses: General.
20RTC_CLKDigital_IOSignal terminal RTC_CLK (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: RTC_CLK. Supported peripheral buses: RTC/CLK.
21GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
22GPIO8Digital_IOSignal terminal GPIO8 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO8. Supported peripheral buses: General.
23SPI_SCKDigital_IOSignal terminal SPI_SCK (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPICLOCKPIN. Supported peripheral buses: SPI.
24SPI_MISODigital_IOSignal terminal SPI_MISO (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPIMISO. Supported peripheral buses: SPI.
25SPI_SSNDigital_IOSignal terminal SPI_SSN (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPI_SSN. Supported peripheral buses: SPI.
26SPI_MOSIDigital_IOSignal terminal SPI_MOSI (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPIMOSI. Supported peripheral buses: SPI.
27GPIO7Digital_IOSignal terminal GPIO7 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO7. Supported peripheral buses: General.
28GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
29GPIO17Digital_IOSignal terminal GPIO17 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO17. Supported peripheral buses: General.
30GPIO18Digital_IOSignal terminal GPIO18 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO18. Supported peripheral buses: General.
31GPIO19Digital_IOSignal terminal GPIO19 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO19. Supported peripheral buses: General.
32GPIO20Digital_IOSignal terminal GPIO20 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO20. Supported peripheral buses: General.
33IRQNDigital_IOSignal terminal IRQN (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: IRQN. Supported peripheral buses: General.
34I2C_SCLM_Digital_IOSignal terminal I2C_SCLM_ (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: I2C_SCLM_. Supported peripheral buses: I2C.
35I2C_SDAM_Digital_IOSignal terminal I2C_SDAM_ (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: I2C_SDAM_. Supported peripheral buses: I2C.
36GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
37PADDLEVSSGND0V electrical ground return terminal (PADDLEVSS) for internal core logic, I/O drivers, and analog sub-blocks.
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