SMD · 29P
Synchronized Pinout (Symbol / 2D / 3D) (29/29)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | GPIO_6 | I/O | Multiplexed I/O & Peripheral Pin GPIO_6 (General) |
| 2 | I2C_SCL | I/O | Multiplexed I/O & Peripheral Pin I2C_SCL (I2C) |
| 3 | I2C_SDA | I/O | Multiplexed I/O & Peripheral Pin I2C_SDA (I2C) |
| 4 | RESET_N | I | System Enable & Hardware Reset (RESET_N) |
| 5 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 6 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 7 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 8 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 9 | GND_1 | GND | Ground Reference Pin (GND_1) |
| 10 | SPI_CFG | I/O | Multiplexed I/O & Peripheral Pin SPI_CFG (SPI) |
| 11 | WAKE | I/O | Multiplexed I/O & Peripheral Pin WAKE (CAN) |
| 12 | GND_2 | GND | Ground Reference Pin (GND_2) |
| 13 | IRQN | I/O | Multiplexed I/O & Peripheral Pin IRQN (General) |
| 14 | UART_TXD | I/O | Multiplexed I/O & Peripheral Pin UART_TXD (UART) |
| 15 | SPI_MOSI | I/O | Multiplexed I/O & Peripheral Pin SPI_MOSI (SPI) |
| 16 | SPI_SSN | I/O | Multiplexed I/O & Peripheral Pin SPI_SSN (SPI) |
| 17 | SPI_MISO | I/O | Multiplexed I/O & Peripheral Pin SPI_MISO (SPI) |
| 18 | SPI_SCK | I/O | Multiplexed I/O & Peripheral Pin SPI_SCK (SPI) |
| 19 | UART_RXD | I/O | Multiplexed I/O & Peripheral Pin UART_RXD (UART) |
| 20 | VBATT | Power | Power Supply Input (VBATT — 2.7V to 3.6V) |
| 21 | GPIO_1 | I/O | Multiplexed I/O & Peripheral Pin GPIO_1 (General) |
| 22 | CHIP_EN | I/O | Multiplexed I/O & Peripheral Pin CHIP_EN (General) |
| 23 | VDDIO | Power | Power Supply Input (VDDIO — 2.7V to 3.6V) |
| 24 | 1P3V_TP | I/O | Multiplexed I/O & Peripheral Pin 1P3V_TP (General) |
| 25 | GPIO_3 | I/O | Multiplexed I/O & Peripheral Pin GPIO_3 (General) |
| 26 | GPIO_4 | I/O | Multiplexed I/O & Peripheral Pin GPIO_4 (General) |
| 27 | GPIO_5 | I/O | Multiplexed I/O & Peripheral Pin GPIO_5 (General) |
| 28 | GND_3 | GND | Ground Reference Pin (GND_3) |
| 29 | PADDLEGND | GND | Ground Reference Pin (PADDLEGND) |
PIN 1 GPIO_6
I/OMultiplexed I/O & Peripheral Pin GPIO_6 (General)
Design note: GeneralpurposeI/O(1) .
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SMD-28P · 14.80×21.80mm · Pitch 1.02mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for ATWINC1510
P1 · p01_fig01456×280px
P6 · p06_fig011666×1231px
P7 · p07_fig011453×1108px
P28 · p28_fig011651×949px
P28 · p28_fig01P28
P29 · p29_fig011726×871px
P29 · p29_fig021739×951px
P29 · p29_fig02P29
P30 · p30_fig011047×1018px
P30 · p30_fig01P30
P54 · p54_fig011787×2596px
P54 · p54_fig01P54
Technical Specifications & Part Details (ATWINC1510-MR210PB1976)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:ATWINC1510-MR210PB1976 (SMD-28P) is a 28-pin wireless wi-fi / bluetooth le soc module featuring a 21.80 × 14.80 × 2.40 mm mechanical envelope (lead pitch e = 1.02 mm). Rated for 2.7V to 3.6V supply operation across -40°C to +85°C with integrated Wi-Fi, UART, SPI, CAN, I2C interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
21.80 × 14.80 × 2.40 mm (A1=0.00 mm)
Package family: CASTELLATED_MODULE (SMD-28P)
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 1.02 mm (40.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, UART, SPI, CAN, I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol29 auto-grouped pins
IPC-7351B Land Pattern29 pads · Pitch 1.02mm
IPC-7525 60% Solder PasteEPAD 3.70×3.70mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — ATWINC1510 (2)
SMD-28P · 29P
29P21.8×14.8×2.40mmP=1.02mm
ATWINC1510 (SMD-28P)
Mechanical Dimensions & Land Pattern (SMD-28P)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
21.80 × 14.80 mm
Height (A) & Pitch (e)IPC-7351B
A=2.40mm · e=1.02mm
Pad Size (W × L)Level B
0.80 × 2.00 mm
Pins / Total PadsTopology
29P / 29Pad (CASTELLATED_MODULE)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SMD-28P | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — ATWINC1510-MR210PB1976 (SMD-28P)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of ATWINC1510-MR210PB1976 (SMD-28P)?
Manufactured by MICROCHIP, the ATWINC1510-MR210PB1976 is housed in a SMD-28P package with 29 pins and a 1.02 mm lead pitch, supporting a VCC supply range of 2.7V to 3.6V. Key pins include: 1 (GPIO_6: Multiplexed I/O & Peripheral Pin GPIO_6 (General)), 2 (I2C_SCL: Multiplexed I/O & Peripheral Pin I2C_SCL (I2C)), 3 (I2C_SDA: Multiplexed I/O & Peripheral Pin I2C_SDA (I2C)), 4 (RESET_N: System Enable & Hardware Reset (RESET_N)), 5 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).
What are the IPC-7351B PCB Footprint dimensions for ATWINC1510-MR210PB1976?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATWINC1510-MR210PB1976 (SMD-28P) has a nominal body envelope of 14.80 × 21.80 mm, pitch e = 1.02 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 3.70 × 3.70 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATWINC1510-MR210PB1976?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATWINC1510-MR210PB1976 (MICROCHIP, SMD-28P) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (29 pins) & ATWINC1510 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | GPIO_6 | Digital_IO | Signal terminal GPIO_6 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO_6. Supported peripheral buses: General. |
| 2 | I2C_SCL | Digital_IO | Signal terminal I2C_SCL (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: I2C_SCL. Supported peripheral buses: I2C. |
| 3 | I2C_SDA | Digital_IO | Signal terminal I2C_SDA (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: I2C_SDA. Supported peripheral buses: I2C. |
| 4 | RESET_N | Digital_IO | Active-low hardware reset terminal (RESET_N): pulling this pin Low resets the processor core and peripherals. |
| 5 | NC | NC | Signal terminal NC (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 6 | NC | NC | Signal terminal NC (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 7 | NC | NC | Signal terminal NC (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 8 | NC | NC | Signal terminal NC (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 9 | GND_1 | GND | 0V electrical ground return terminal (GND_1) for internal core logic, I/O drivers, and analog sub-blocks. |
| 10 | SPI_CFG | Digital_IO | Signal terminal SPI_CFG (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPI_CFG. Supported peripheral buses: SPI. |
| 11 | WAKE | Digital_IO | Signal terminal WAKE (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: WAKE. Supported peripheral buses: CAN. |
| 12 | GND_2 | GND | 0V electrical ground return terminal (GND_2) for internal core logic, I/O drivers, and analog sub-blocks. |
| 13 | IRQN | Digital_IO | Signal terminal IRQN (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: IRQN. Supported peripheral buses: General. |
| 14 | UART_TXD | Digital_IO | Signal terminal UART_TXD (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: UART_TXD. Supported peripheral buses: UART. |
| 15 | SPI_MOSI | Digital_IO | Signal terminal SPI_MOSI (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPIMOSI. Supported peripheral buses: SPI. |
| 16 | SPI_SSN | Digital_IO | Signal terminal SPI_SSN (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPI_CLIENT. Supported peripheral buses: SPI. |
| 17 | SPI_MISO | Digital_IO | Signal terminal SPI_MISO (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPIMISO. Supported peripheral buses: SPI. |
| 18 | SPI_SCK | Digital_IO | Signal terminal SPI_SCK (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPICLOCK. Supported peripheral buses: SPI. |
| 19 | UART_RXD | Digital_IO | Signal terminal UART_RXD (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: UART_RXD. Supported peripheral buses: UART. |
| 20 | VBATT | Power_In | Primary positive power supply input (VBATT) operating in the 2.7V to 3.6V domain (Max rating: 3.6V). |
| 21 | GPIO_1 | Digital_IO | Signal terminal GPIO_1 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO_1. Supported peripheral buses: General. |
| 22 | CHIP_EN | Digital_IO | Signal terminal CHIP_EN (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: CHIP_EN. Supported peripheral buses: General. |
| 23 | VDDIO | Power_In | Primary positive power supply input (VDDIO) operating in the 2.7V to 3.6V domain (Max rating: 3.6V). |
| 24 | 1P3V_TP | Digital_IO | Signal terminal 1P3V_TP (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: 1P3V_TP. Supported peripheral buses: General. |
| 25 | GPIO_3 | Digital_IO | Signal terminal GPIO_3 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO_3. Supported peripheral buses: General. |
| 26 | GPIO_4 | Digital_IO | Signal terminal GPIO_4 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO_4. Supported peripheral buses: General. |
| 27 | GPIO_5 | Digital_IO | Signal terminal GPIO_5 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO_5. Supported peripheral buses: General. |
| 28 | GND_3 | GND | 0V electrical ground return terminal (GND_3) for internal core logic, I/O drivers, and analog sub-blocks. |
| 29 | PADDLEGND | GND | 0V electrical ground return terminal (PADDLEGND) for internal core logic, I/O drivers, and analog sub-blocks. |