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C701330 (WIFI-SMD_ESP32-S2-WROOM-I-1) — Symbol, Footprint IPC-7351B & 3D STEP Model

C701330

SemiconductorWIFI-SMD_ESP32-S2-WROOM-I-1 · 43 Pins · Pitch 1.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C701330 (WIFI-SMD_ESP32-S2-WROOM-I-1)1GND23V33IO04IO15IO26IO37IO48IO59IO610IO711IO812IO913IO1014IO1115IO1216IO1317IO1418IO1519IO1620IO1721IO1822IO1943EP42GND41EN40IO4639IO4538RXD037TXD036IO4235IO4134IO4033IO3932IO3831IO3730IO3629IO3528IO3427IO3326GND25IO2624IO2123IO20Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.233.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0mm
2. 2D FOOTPRINT
ANTENNA KEEPOUT (6.7mm)434343434343434343424140393837363534333231302928272625242322212019181716151413121110987654321E=18.00mm · Pitch e=1.50mmD=31.00mm-18-16-14-12-10-8-6-4-2024681012141618242220181614121086420-2-4-6-8-10-12-14-16-18-20-22-24mm
3. 3D CAD MODEL
Package Body: 18.00mm × 31.00mm · Pitch: 1.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (43/43)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GNDGNDGround Reference Pin (GND)
23V3PowerPower Supply Input (3V3 — 3.3V / 5.0V Standard Logic)
3IO0I/OMultiplexed I/O & Peripheral Pin IO0 (General)
4IO1I/OMultiplexed I/O & Peripheral Pin IO1 (General)
5IO2I/OMultiplexed I/O & Peripheral Pin IO2 (General)
6IO3I/OMultiplexed I/O & Peripheral Pin IO3 (General)
7IO4I/OMultiplexed I/O & Peripheral Pin IO4 (General)
8IO5I/OMultiplexed I/O & Peripheral Pin IO5 (General)
9IO6I/OMultiplexed I/O & Peripheral Pin IO6 (General)
10IO7I/OMultiplexed I/O & Peripheral Pin IO7 (General)
11IO8I/OMultiplexed I/O & Peripheral Pin IO8 (General)
12IO9I/OMultiplexed I/O & Peripheral Pin IO9 (General)
13IO10I/OMultiplexed I/O & Peripheral Pin IO10 (General)
14IO11I/OMultiplexed I/O & Peripheral Pin IO11 (General)
15IO12I/OMultiplexed I/O & Peripheral Pin IO12 (General)
16IO13I/OMultiplexed I/O & Peripheral Pin IO13 (General)
17IO14I/OMultiplexed I/O & Peripheral Pin IO14 (General)
18IO15I/OMultiplexed I/O & Peripheral Pin IO15 (General)
19IO16I/OMultiplexed I/O & Peripheral Pin IO16 (General)
20IO17I/OMultiplexed I/O & Peripheral Pin IO17 (General)
21IO18I/OMultiplexed I/O & Peripheral Pin IO18 (General)
22IO19I/OMultiplexed I/O & Peripheral Pin IO19 (General)
23IO20I/OMultiplexed I/O & Peripheral Pin IO20 (General)
24IO21I/OMultiplexed I/O & Peripheral Pin IO21 (General)
25IO26I/OMultiplexed I/O & Peripheral Pin IO26 (General)
26GNDGNDGround Reference Pin (GND)
27IO33I/OMultiplexed I/O & Peripheral Pin IO33 (General)
28IO34IInput-Only Pin IO34 (General)
29IO35IInput-Only Pin IO35 (General)
30IO36IInput-Only Pin IO36 (General)
31IO37IInput-Only Pin IO37 (General)
32IO38IInput-Only Pin IO38 (General)
33IO39IInput-Only Pin IO39 (General)
34IO40I/OMultiplexed I/O & Peripheral Pin IO40 (General)
35IO41I/OMultiplexed I/O & Peripheral Pin IO41 (General)
36IO42I/OMultiplexed I/O & Peripheral Pin IO42 (General)
37TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
38RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
39IO45I/OMultiplexed I/O & Peripheral Pin IO45 (General)
40IO46I/OMultiplexed I/O & Peripheral Pin IO46 (General)
41ENISystem Enable & Hardware Reset (EN)
42GNDGNDGround Reference Pin (GND)
43EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 GND
GND
Ground Reference Pin (GND)
Design note: 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C701330 (Semiconductor · WIFI-SMD_ESP32-S2-WROOM-I-1)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C701330 (WIFI-SMD_ESP32-S2-WROOM-I-1) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C701330 (WIFI-SMD_ESP32-S2-WROOM-I-1) - 2. Standard Pinout (Top View)
True package pinout (43 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C701330 (WIFI-SMD_ESP32-S2-WROOM-I-1) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C701330 (WIFI-SMD_ESP32-S2-WROOM-I-1) - 4. Package Dimensions (D×E×A)
WIFI-SMD_ESP32-S2-WROOM-I-1 · 18.00×31.00mm · Pitch 1.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
C701330 (WIFI-SMD_ESP32-S2-WROOM-I-1) - 5. Recommended Land Pattern
IPC-7351B Footprint (51 Pads)Expand ›
6. Application SchematicSCHEMATIC
C701330 (WIFI-SMD_ESP32-S2-WROOM-I-1) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C701330)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:C701330 (WIFI-SMD_ESP32-S2-WROOM-I-1) is a 42-pin wireless wi-fi / bluetooth le soc module featuring a 31.00 × 18.00 × 3.10 mm mechanical envelope (lead pitch e = 1.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
31.00 × 18.00 × 3.10 mm (A1=0.00 mm)
Package family: CASTELLATED_MODULE (WIFI-SMD_ESP32-S2-WROOM-I-1)
Pin Count & Lead PitchN / e
42 Pins | Pitch e = 1.50 mm (59.1 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol43 auto-grouped pins
OK
IPC-7351B Land Pattern51 pads · Pitch 1.50mm
OK
IPC-7525 60% Solder PasteEPAD 4.10×4.10mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WIFI-SMD_ESP32-S2-WROOM-I-1)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
31.00 × 18.00 mm
Height (A) & Pitch (e)IPC-7351B
A=3.10mm · e=1.50mm
Pad Size (W × L)Level B
1.00 × 1.80 mm
Pins / Total PadsTopology
43P / 51Pad (CASTELLATED_MODULE)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WIFI-SMD_ESP32-S2-WROOM-I-1
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C701330 (WIFI-SMD_ESP32-S2-WROOM-I-1)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C701330 (WIFI-SMD_ESP32-S2-WROOM-I-1)?

Manufactured by Semiconductor, the C701330 is housed in a WIFI-SMD_ESP32-S2-WROOM-I-1 package with 43 pins and a 1.50 mm lead pitch. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (3V3: Power Supply Input (3V3 — 3.3V / 5.0V Standard Logic)), 3 (IO0: Multiplexed I/O & Peripheral Pin IO0 (General)), 4 (IO1: Multiplexed I/O & Peripheral Pin IO1 (General)), 5 (IO2: Multiplexed I/O & Peripheral Pin IO2 (General)), 6 (IO3: Multiplexed I/O & Peripheral Pin IO3 (General)).

What are the IPC-7351B PCB Footprint dimensions for C701330?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C701330 (WIFI-SMD_ESP32-S2-WROOM-I-1) has a nominal body envelope of 18.00 × 31.00 mm, pitch e = 1.50 mm, and 51 copper pads plus a central exposed thermal pad (EPAD) of 4.10 × 4.10 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C701330?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C701330 (Semiconductor, WIFI-SMD_ESP32-S2-WROOM-I-1) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (43 pins) & ESP32-S2-WROOM Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
23V3Power_InPrimary positive power supply input (3V3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3IO0Digital_IOSignal terminal IO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO0. Supported peripheral buses: General.
4IO1Digital_IOSignal terminal IO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO1. Supported peripheral buses: General.
5IO2Digital_IOSignal terminal IO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO2. Supported peripheral buses: General.
6IO3Digital_IOSignal terminal IO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO3. Supported peripheral buses: General.
7IO4Digital_IOSignal terminal IO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO4. Supported peripheral buses: General.
8IO5Digital_IOSignal terminal IO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO5. Supported peripheral buses: General.
9IO6Digital_IOSignal terminal IO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO6. Supported peripheral buses: General.
10IO7Digital_IOSignal terminal IO7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO7. Supported peripheral buses: General.
11IO8Digital_IOSignal terminal IO8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO8. Supported peripheral buses: General.
12IO9Digital_IOSignal terminal IO9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO9. Supported peripheral buses: General.
13IO10Digital_IOSignal terminal IO10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO10. Supported peripheral buses: General.
14IO11Digital_IOSignal terminal IO11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO11. Supported peripheral buses: General.
15IO12Digital_IOSignal terminal IO12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO12. Supported peripheral buses: General.
16IO13Digital_IOSignal terminal IO13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO13. Supported peripheral buses: General.
17IO14Digital_IOSignal terminal IO14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO14. Supported peripheral buses: General.
18IO15Digital_IOSignal terminal IO15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO15. Supported peripheral buses: General.
19IO16Digital_IOSignal terminal IO16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO16. Supported peripheral buses: General.
20IO17Digital_IOSignal terminal IO17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO17. Supported peripheral buses: General.
21IO18Digital_IOSignal terminal IO18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO18. Supported peripheral buses: General.
22IO19Digital_IOSignal terminal IO19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO19. Supported peripheral buses: General.
23IO20Digital_IOSignal terminal IO20 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO20. Supported peripheral buses: General.
24IO21Digital_IOSignal terminal IO21 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO21. Supported peripheral buses: General.
25IO26Digital_IOSignal terminal IO26 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO26. Supported peripheral buses: General.
26GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
27IO33Digital_IOSignal terminal IO33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO33. Supported peripheral buses: General.
28IO34Digital_IOSignal terminal IO34 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO34. Supported peripheral buses: General.
29IO35Digital_IOSignal terminal IO35 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO35. Supported peripheral buses: General.
30IO36Digital_IOSignal terminal IO36 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO36. Supported peripheral buses: General.
31IO37Digital_IOSignal terminal IO37 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO37. Supported peripheral buses: General.
32IO38Digital_IOSignal terminal IO38 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO38. Supported peripheral buses: General.
33IO39Digital_IOSignal terminal IO39 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO39. Supported peripheral buses: General.
34IO40Digital_IOSignal terminal IO40 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO40. Supported peripheral buses: General.
35IO41Digital_IOSignal terminal IO41 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO41. Supported peripheral buses: General.
36IO42Digital_IOSignal terminal IO42 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO42. Supported peripheral buses: General.
37TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
38RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
39IO45Digital_IOSignal terminal IO45 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO45. Supported peripheral buses: General.
40IO46Digital_IOSignal terminal IO46 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO46. Supported peripheral buses: General.
41ENDigital_IOChip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset.
42GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
43EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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