HMC1133LP5ETR (STM-32(5x5)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model | chipdocs.org

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1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
2	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
3	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
4	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
5	RF1	I/O	Multiplexed I/O & Peripheral Pin RF1 (General)
6	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
7	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
8	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
9	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
10	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
11	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
12	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
13	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
14	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
15	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
16	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
17	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
18	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
19	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
20	RF2	I/O	Multiplexed I/O & Peripheral Pin RF2 (General)
21	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
22	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
23	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
24	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
25	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
26	BIT6	I/O	Multiplexed I/O & Peripheral Pin BIT6 (General)
27	BIT5	I/O	Multiplexed I/O & Peripheral Pin BIT5 (General)
28	BIT4	I/O	Multiplexed I/O & Peripheral Pin BIT4 (General)
29	BIT3	I/O	Multiplexed I/O & Peripheral Pin BIT3 (General)
30	BIT2	I/O	Multiplexed I/O & Peripheral Pin BIT2 (General)
31	BIT1	I/O	Multiplexed I/O & Peripheral Pin BIT1 (General)
32	VSS	GND	Ground Reference Pin (VSS)
33	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 NC

I/O

Multiplexed I/O & Peripheral Pin NC (General)

Design note: Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

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PDF VIEWEROfficial Datasheet Document: HMC1133LP5ETR (ADI · STM-32(5x5))

Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below

1. Realistic 3D PackageREPRESENTATIVE

HMC1133LP5ETR (STM-32(5x5)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

HMC1133LP5ETR (STM-32(5x5)) - 2. Standard Pinout (Top View)

True package pinout (33 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

HMC1133LP5ETR (STM-32(5x5)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

HMC1133LP5ETR (STM-32(5x5)) - 4. Package Dimensions (D×E×A)

STM-32(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

HMC1133LP5ETR (STM-32(5x5)) - 5. Recommended Land Pattern

IPC-7351B Footprint (33 Pads)Expand ›

6. Application SchematicSCHEMATIC

HMC1133LP5ETR (STM-32(5x5)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)

Showing 1–12 of 13 uncropped original figures for HMC1133

P1 · p01_fig01787×790px

HMC1133LP5ETR (STM-32(5x5)) — Electrical Specifications TA = +25° C, Vss= -5V, Vdd= +5V , BIT1 to BIT6 = 0/ +5V, 50 Ohm System

Electrical Specifications TA = +25° C, Vss= -5V, Vdd= +5V , BIT1 to BIT6 = 0/ +5V, 50 Ohm System

P1 · p01_fig01P1

HMC1133LP5ETR (STM-32(5x5)) — Datasheet Page 1 (p01_fig01)

Datasheet Page 1 (p01_fig01)

P2 · p02_fig01809×642px

HMC1133LP5ETR (STM-32(5x5)) — Phase Error, Major States Only Input Return Loss, Major States Only

Phase Error, Major States Only Input Return Loss, Major States Only

P2 · p02_fig02778×631px

HMC1133LP5ETR (STM-32(5x5)) — Phase Error, Major States Only Input Return Loss, Major States Only

Phase Error, Major States Only Input Return Loss, Major States Only

P2 · p02_fig031766×887px

HMC1133LP5ETR (STM-32(5x5)) — RETURN LOSS (dB)

RETURN LOSS (dB)

P2 · p02_fig041771×913px

HMC1133LP5ETR (STM-32(5x5)) — -40

-40

P3 · p03_fig011727×641px

HMC1133LP5ETR (STM-32(5x5)) — Input IP2, Major States Only Input P1dB, Major States Only

Input IP2, Major States Only Input P1dB, Major States Only

P3 · p03_fig021779×894px

HMC1133LP5ETR (STM-32(5x5)) — -4

-4

P3 · p03_fig031779×907px

HMC1133LP5ETR (STM-32(5x5)) — 15

15

P5 · p05_fig011478×965px

HMC1133LP5ETR (STM-32(5x5)) — v01.1216 GaAs MMIC 6-BIT DIGITAL PHASE SHIFTER, 4.8 - 6.2 GHz

v01.1216 GaAs MMIC 6-BIT DIGITAL PHASE SHIFTER, 4.8 - 6.2 GHz

P5 · p05_fig021777×1033px

HMC1133LP5ETR (STM-32(5x5)) — [1] Max peak reflow temperature of 260 °C [2] 4-Digit lot number XXXX

[1] Max peak reflow temperature of 260 °C [2] 4-Digit lot number XXXX

P5 · p05_fig01P5

HMC1133LP5ETR (STM-32(5x5)) — Datasheet Page 5 (p05_fig01)

Datasheet Page 5 (p05_fig01)

Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (HMC1133LP5ETR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:HMC1133LP5ETR (STM-32(5x5)) is a 32-pin standard electronic & interconnect component featuring a 5.80 × 6.20 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 85C -40C with integrated Standard I/O / Passive interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

85C -40C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

6.2 GHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

5.80 × 6.20 × 0.90 mm (A1=0.10 mm)

Package family: OTHER (STM-32(5x5))

Pin Count & Lead PitchN / e

32 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Standard I/O / Passive

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol33 auto-grouped pins

OK

IPC-7351B Land Pattern33 pads · Pitch 0.50mm

OK

IPC-7525 60% Solder PasteEPAD 3.80×3.80mm windowed grid

OK

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

OK

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (STM-32(5x5))

Extracted from Datasheet & IPC-7351B Normalized

mm

Package Body (D × E)Nominal

5.00 × 5.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.90mm · e=0.50mm

Pad Size (W × L)Level B

0.30 × 0.80 mm

Pins / Total PadsTopology

33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit STM-32(5x5)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — HMC1133LP5ETR (STM-32(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of HMC1133LP5ETR (STM-32(5x5))?

Manufactured by ADI, the HMC1133LP5ETR is housed in a STM-32(5x5) package with 33 pins and a 0.50 mm lead pitch. Key pins include: 1 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 2 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 5 (RF1: Multiplexed I/O & Peripheral Pin RF1 (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).

What are the IPC-7351B PCB Footprint dimensions for HMC1133LP5ETR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), HMC1133LP5ETR (STM-32(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.80 × 3.80 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for HMC1133LP5ETR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for HMC1133LP5ETR (ADI, STM-32(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & HMC1133 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
2	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
3	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
4	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
5	RF1	RF_50Ohm	Signal terminal RF1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RF1. Supported peripheral buses: General.
6	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
7	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
8	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
9	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
10	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
11	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
12	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
13	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
15	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
16	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
17	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
18	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
19	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
20	RF2	RF_50Ohm	Signal terminal RF2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RF2. Supported peripheral buses: General.
21	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
22	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
23	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
24	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
25	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
26	BIT6	Digital_IO	Signal terminal BIT6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BIT6. Supported peripheral buses: General.
27	BIT5	Digital_IO	Signal terminal BIT5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BIT5. Supported peripheral buses: General.
28	BIT4	Digital_IO	Signal terminal BIT4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BIT4. Supported peripheral buses: General.
29	BIT3	Digital_IO	Signal terminal BIT3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BIT3. Supported peripheral buses: General.
30	BIT2	Digital_IO	Signal terminal BIT2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BIT2. Supported peripheral buses: General.
31	BIT1	Digital_IO	Signal terminal BIT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BIT1. Supported peripheral buses: General.
32	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
33	EP	GND	Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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